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HD64F2145 Datasheet(PDF) 313 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 313 Page - Renesas Technology Corp |
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313 / 829 page  Rev. 2.0, 08/02, page 273 of 788 Bit Bit Name Initial Value R/W Description 4 3 CCLR1 CCLR0 0 0 R/W R/W Counter Clear 1, 0 These bits select the method by which the timer counter is cleared. 00: Clearing is disabled 01: Cleared on compare-match A 10: Cleared on compare-match B 11: Cleared on rising edge of external reset input 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 These bits select the clock input to TCNT and count condition, together with the ICKS1 and ICKS0 bits in STCR. For details, see table 12.2. Table 12.2 Clock Input to TCNT and Count Condition TCR STCR Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description 0 0 0 — — Disables clock input 0 0 1 — 0 Increments at falling edge of internal clock ø/8 0 0 1 — 1 Increments at falling edge of internal clock ø/2 0 1 0 — 0 Increments at falling edge of internal clock ø/64 0 1 0 — 1 Increments at falling edge of internal clock ø/32 0 1 1 — 0 Increments at falling edge of internal clock ø/1024 0 1 1 — 1 Increments at falling edge of internal clock ø/256 TMR_0 1 0 0 — — Increments at overflow signal from TCNT_1* |
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