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TLE9461ES Datasheet(PDF) 36 Page - Infineon Technologies AG

Part # TLE9461ES
Description  Lite CAN SBC Family
PDF  140 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

TLE9461ES Datasheet(HTML) 36 Page - Infineon Technologies AG

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TLE9461ES
Lite CAN SBC Family
System Features
Datasheet
36
Rev.1.1
2019-09-27
The Cyclic Sense function is disabled at the following conditions (WK/VSENSE is automatically switched to
Static Sense):
• in case SBC Fail-Safe Mode is entered: The HS GPIO switch is disabled and the wake pin is changed to static
sensing. An unintended wake-up event could be triggered when the WK/VSENSE input is changed to static
sensing.
• In SBC Normal, Stop, or Sleep Mode in case of an overcurrent or overtemperature (TSD2) event: the HS
GPIO switch is disabled
Note:
The internal timer for Cyclic Sense is not cleared automatically in case the HS switch is turned Off due
to above mentioned failures. The timer is only cleared during SBC Restart Mode. This must be
considered to avoid a loss of wake-up events, especially before entering SBC Sleep Mode, i.e. the
software must ensure that at least another wake source is active or re-enable the GPIO HS again.
5.2.1.2
Cyclic Sense in Low-Power Mode
If Cyclic Sense is intended for use in SBC Stop or SBC Sleep Mode, it is necessary to activate Cyclic Sense in SBC
Normal Mode before going to the low-power mode. A wake-up event due to Cyclic Sense sets the bit WK_WU.
In SBC Stop Mode a wake-up event triggers an interrupt, in SBC Sleep Mode the wake-up event moves the
device via SBC Restart Mode to SBC Normal Mode.
Before returning to SBC Sleep Mode, the wake status registers WK_STAT_0 and WK_STAT_1 need to be
cleared. Trying to go to SBC Sleep Mode with uncleared wake flags leads to a direct wake-up from Sleep Mode
by going via Restart Mode to Normal Mode and triggering of RSTN.
The intention of this behavior is to prevent a loss of a wake-up event during the transition.
Note:
if an over-current shutdown occurs at the GPIO HS in SBC Sleep Mode, while configured as Cyclic
Sense, and Cyclic Sense is the only wake source, then the SBC leaves SBC Sleep Mode immediately
because there is no other wake source available .
5.2.2
Cyclic Wake
The Cyclic Wake feature is intended to reduce the quiescent current of the device in the application. The
internal timer wakes the load, e.g. the microcontroller, periodically while it is in a low-power mode for the
most of the time.
For the Cyclic Wake feature the timer is configured as an internal wake-up source and periodically triggers an
interrupt on INTN in SBC Normal and SBC Stop Mode. During SBC Sleep Mode, the timer periodically wakes
the device (via SBC Restart to SBC Normal Mode).
The correct sequence to configure the Cyclic Wake is shown in Figure 11. The sequence is as follows:
• Enable Timer as a wake-up source in the register WK_CTRL_0,
• Configure the period of the Timer. Also an On-time (any value except ‘000’ or ‘110’ or ‘111’) must be
selected to start the Cyclic Wake function.



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