TLE9461ES datasheet(97/140 Pages) INFINEON

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TLE9461ES

Lite CAN SBC Family

Serial Peripheral Interface

Datasheet

Rev.1.1

2019-09-27

Serial Peripheral Interface

The Serial Peripheral Interface is the communication link between the SBC and the microcontroller.

The TLE9461ES is supporting multi-slave operation in full-duplex mode with 16-bitdata access.

The SPI behavior for the different SBC Modes is as follows:

• The SPI is enabled in SBC Init, Normal and Stop Mode

• The SPI is disabled in SBC Sleep, Restart and Fail-Safe Mode

13.1

SPI Block Description

The Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK provided

by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 39 with a

16-bit data access example).

The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), Low active. After

the CSN input returns from Low to High, the word that has been read is interpreted according to the content.

The SDO output switches to tristate status (high impedance) at this point, thereby releasing the SDO bus for

other use. The state of SDI is shifted into the input register with every falling edge on CLK. The state of SDO is

shifted out of the output register after every rising edge on CLK. The SPI of the SBC is not daisy chain capable.

Figure 39 SPI Data Transfer Timing (note the reversed order of LSB and MSB shown in this figure

compared to the register description)

1 2 3 4 5 6 7 8 9 10

0 1 2 3 4 5 6

11 12 13 14

7 8 9 10

CSN high to low: SDO is enabled. Status information transferred to output shift register

CSN low to high: data from shift register is transferred to output functions

SDI: will accept data on the falling edge of CLK signal

SDO: will change state on the rising edge of CLK signal

Actual status

11 12 13 14

Actual data

New data

New status

SDO

SDI

CSN

CLK

time

ERR

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