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TLE9461ES Datasheet(PDF) 101 Page - Infineon Technologies AG |
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TLE9461ES Datasheet(HTML) 101 Page - Infineon Technologies AG |
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101 / 140 page ![]() TLE9461ES Lite CAN SBC Family Serial Peripheral Interface Datasheet 101 Rev.1.1 2019-09-27 Figure 40 SPI Operation Mode 13.4 SPI Bit Mapping The following figures show the mapping of the registers and the SPI bits of the respective registers. The Control Registers ‘000 0000’ to ‘001 1110’ are Read/Write Register. Depending on bit 7 the bits are only read (setting bit 7 to ‘0’) or also written (setting bit 7 to ‘1’). The new setting of the bit after a write can be seen with a new read / write command. The registers ‘100 0000’ to ‘111 1110’ are Status Registers and can be read or read with clearing the bit (if possible) depending on bit 7. To clear a Data Byte of one of the Status Registers bit 7 must be set to ‘1’. The registers WK_LVL_STAT, and FAM_PROD_STAT are an exception as they show the actual voltage level at the respective WK pin (Low/High), or a fixed family/ product ID respectively and can thus not be cleared. It is recommended for proper diagnosis to clear respective status bits for wake-up events or failure. However, in general it is possible to enable drivers without clearing the respective failure flags. When changing to a different SBC Mode, certain configurations bits is cleared automatically or modified: • The SBC Mode bits are updated to the actual status, e.g. when returning to Normal Mode • When changing to a low-power mode (Stop/Sleep), the diagnosis bits of the switches and transceivers are not cleared. FO will stay activated if it was triggered before. • When changing to SBC Stop Mode, the CAN control bits will not be modified. • When changing to SBC Sleep Mode, the CAN control bits is modified if they were not Off or Wake Capable before. • VCC2 will stay On when going to Sleep-/Stop Mode (configuration can only be done in Normal Mode). Diagnosis is active. In case of a failure the regulator is turned Off and no wake-up is issued. 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 Data Bits DI Address Bits x x x x x x x x R/W 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 Data Bits DO Status Information Field x x x x x x x x Register content of selected address LSB MSB time LSB is sent first in SPI message |
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