Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

NTP53X2 Datasheet(PDF) 40 Page - NXP Semiconductors

Part # NTP53X2
Description  NTAG 5 link - NFC Forum-compliant I2C bridge
PDF  133 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

NTP53X2 Datasheet(HTML) 40 Page - NXP Semiconductors

Back Button NTP53X2 Datasheet HTML 36Page - NXP Semiconductors NTP53X2 Datasheet HTML 37Page - NXP Semiconductors NTP53X2 Datasheet HTML 38Page - NXP Semiconductors NTP53X2 Datasheet HTML 39Page - NXP Semiconductors NTP53X2 Datasheet HTML 40Page - NXP Semiconductors NTP53X2 Datasheet HTML 41Page - NXP Semiconductors NTP53X2 Datasheet HTML 42Page - NXP Semiconductors NTP53X2 Datasheet HTML 43Page - NXP Semiconductors NTP53X2 Datasheet HTML 44Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 40 / 133 page
background image
NXP Semiconductors
NTP53x2
NTAG 5 link - NFC Forum-compliant I2C bridge
NTP53x2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 3.3 — 3 July 2020
COMPANY PUBLIC
544533
40 / 133
NOTE: I2C master is only available for NTP5332.
Table 62. I2C Master Clock Settings Configuration Location (I2C_MASTER_CONFIG)
Block Address
NFC
I2C
Byte 0
Byte 1
Byte 2
Byte 3
3Eh
103Eh
I2C_SLAVE_ADDR
I2C_SLAVE_CONFIG
I2C_MASTER_
SCL_LOW
I2C_MASTER_
SCL_HIGH
Table 63. I2C Master Clock Configuration Definition (I2C_MASTER_SCL_LOW)
Bit
Name
Default
Value
Description
7
RFU
6 to 0
I2C_MASTER_SCL_LOW
09h
I2C master configuration SCL low period. Default: 400 kHz,
41%duty cycle.
Table 64. I2C Master Clock Configuration Definition (I2C_MASTER_SCL_HIGH)
Bit
Name
Default
Value
Description
7
RFU
6 to 0
I2C_MASTER_SCL_HIGH
02h
I2C master configuration SCL HIGH period. Default: 400
kHz, 41%duty cycle.
8.1.3.22 Device security configuration bytes
NTAG 5 link features scale-able security. The level of security can be selected with
DEV_SEC_CONFIG byte.
SRAM_CONF_PROT is described in Section 8.1.3.23.
PP_AREA_1 is described in Section 8.1.3.24.
Table 65. Device Security Configuration Byte location
Block Address
NFC
I2C
Byte 0
Byte 1
Byte 2
Byte 3
3Fh
103Fh
DEV_SEC_CONFIG
SRAM_CONF_PROT
PP_AREA_1 (LSB)
PP_AREA_1 (MSB)
The IC security features can be enabled or disabled or can choose different security
options available from NFC perspective:
• AES authentication scheme
• Plain password feature
Table 66. Device Security Byte Definition (DEV_SEC_CONFIG)
Bit
Name
Value
Description
010b
block 3Fh with device security configuration bytes is locked
101b
block 3Fh is writeable (default)
7 to 5
Security Lock
other
RFU



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com