TMS320F28375DPZP datasheet(122/226 Pages) TI

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8.10.3.1 Buffered DAC Electrical Data and Timing

Section 8.10.3.1.1 shows the buffered DAC electrical characteristics. Figure 8-45 shows the buffered DAC offset.

Figure 8-46 shows the buffered DAC gain. Figure 8-47 shows the buffered DAC linearity.

8.10.3.1.1 Buffered DAC Electrical Characteristics

over recommended operating conditions (unless otherwise noted)(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power-up time

500(8)

µs

Offset error

Midpoint

–10

Gain error(2)

–2.5

2.5

% of FSR

DNL(3)

Endpoint corrected

> –1

±0.4

LSB

INL

Endpoint corrected

–5

±2

LSB

DACOUTx settling time

Settling to 2 LSBs after 0.3V-to-3V

transition

µs

Resolution

bits

Voltage output range(4)

0.3

VDDA – 0.3

Capacitive load

Output drive capability

100

Resistive load

Output drive capability

kΩ

RPD pulldown resistor

kΩ

Reference voltage(5)

VDAC or VREFHI

2.4

2.5 or 3.0

VDDA

Reference input resistance(6)

VDAC or VREFHI

170

kΩ

Output noise

Integrated noise from 100 Hz to 100 kHz

500

µVrms

Noise density at 10 kHz

711

nVrms/√Hz

Glitch energy

1.5

V-ns

PSRR(7)

DC up to 1 kHz

100 kHz

SNR

1020 Hz

THD

1020 Hz

–63

SFDR

1020 Hz, including harmonics and spurs

dBc

1020 Hz, including only spurs

104

(1)

Typical values are measured with VREFHI = 3.3 V unless otherwise noted. Minimum and Maximum values are tested or characterized

with VREFHI = 2.5 V.

(2)

Gain error is calculated for linear output range.

(3)

The DAC output is monotonic.

(4)

This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear

due to the buffer.

(5)

For best PSRR performance, VDAC or VREFHI should be less than VDDA.

(6)

Per active Buffered DAC module.

(7)

VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.

(8)

See the "Analog Bandgap References" advisory of the TMS320F2837xD Dual-Core MCUs Silicon Errata .

Note

The VDAC pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VDAC

pin exceeds this level, a blocking circuit may activate, and the internal value of VDAC may float to 0 V

internally, giving improper DAC output.

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

www.ti.com

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TMS320F28375DPZP Datasheet(PDF) 122 Page - Texas Instruments

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