MCIMX503CVM8B datasheet(135/136 Pages) NXP

135 / 136 page

Revision History

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

135

Rev. 1

10/2011

• Table 5, "Special Signal Considerations," on page 17 changed CHRG_DET_B to CHGR_DET_B.

• Table 5, "Special Signal Considerations," on page 17 in the CHGR_DET_B signal remarks, added “The

maximum current leakage at this pin is 8.5

μA.”

• Table 5, "Special Signal Considerations," on page 17 in the JTAG_MOD remarks, changed “pull-down”

to “pull-up, by default” and added “If JTAG port is not needed, the internal pull-up can be disabled in order

to reduce supply current to the pin.”

• Table 14, "Maximum Supply Current Consumption—ARM CLK = 800 MHz," on page 27 in the 11th row

under the Supply column, changed VDDO2P5 to VDDO25.

• Table 78, "VBUS Comparators Thresholds," on page 101 changed CHRG_DET_B to CHGR_DET_B.

• Table 5, "Special Signal Considerations," on page 17 for 416 MAPBGA, DRAM_SDCLK_0 pin number

was changed to N24 and DRAM_SDCLK_0_B pin number was changed to M24.

• Table 5, "Special Signal Considerations," on page 17 for 416 MAPBGA, DRAM_SDCLK_1 pin number

was changed to T20 and DRAM_SDCLK_1_B pin number was changed to R20.

• Table 5, "Special Signal Considerations," on page 17 for 416 MAPBGA, DRAM_SDQS0 pin number was

changed to P23 and DRAM_SDQS0_B pin number was changed to P24.

• Table 5, "Special Signal Considerations," on page 17 changed pad type of pin DRAM_CALIBRATION to

DRAMCALIB.

• Table 5, "Special Signal Considerations," on page 17 changed pad type of pins DRAM_SDCLK_0,

DRAM_SDCLK_0_B, DRAM_SDCLK_1, DRAM_SDCLK_1_B, DRAM_SDQS0, DRAM_SDQS0_B,

DRAM_SDQS1, DRAM_SDQS1_B, DRAM_SDQS2, DRAM_SDQS2_B, DRAM_SDQS3, and

DRAM_SDQS3_B to DRAMCLK.

Rev. 0

07/2011 Initial release.

Table 86. i.MX50 Data Sheet Document Revision History (continued)

Rev.

Number

Date

Substantive Change(s)

MCIMX503CVM8B Datasheet(PDF) 135 Page - NXP Semiconductors