H5AN8G6NAFR-RDC datasheet(8/45 Pages) HYNIX

8 / 45 page

Rev. 1.2 / Jul.2017

Pin Functional Description

Symbol

Type

Function

CK_t, CK_c

Input

Clock: CK_t and CK_c are differential clock inputs. All address and control input signals

are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.

CKE, (CKE1)

Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and

device input buffers and output drivers. Taking CKE Low provides Precharge Power-

Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in

any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have

become stable during the power on and initialization sequence, they must be maintained

during all operations (including Self-Refresh). CKE must be maintained high throughout

read and write accesses. Input buffers, excluding CK, CK_c, ODT and CKE, are disabled

during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh.

CS_n, (CS1_n)

Input

Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for

external Rank selection on systems with multiple Ranks. CS_n is considered part of the

command code.

C0,C1,C2

Input

Chip ID: Chip ID is only used for 3DS for 2,4,8high stack via TSV to select each slice of

stacked compnent. Chip ID is considered part of the command code.

ODT, (ODT1)

Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal to

the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and

DM_n/DBI_n/TDQS_t,NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in

MR1) signal for x8 configurations. For x16 configuration ODT is applied to each DQ,

DQSU_c, DQSU_t, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT pin will be

ignored if MR1 is programmed to disable RTT_NOM.

ACT_n

Input

Activation Command Input: ACT_n defines the Activation command being entered along

with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as

Row Address A16, A15 and A14.

RAS_n/A16,

CAS_n/A15,

WE_n/A14

Input

Command Inputs RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the

command being entered. Those pins have multi function. For example, for activation

with ACT_n Low, those are Addressing like A16,A15 and A14 but for non-activation com-

mand with ACT_n High, those are Command pins for Read, Write and other command

defined in command truth table.

DM_n/DBI_n/

TDQS_t,

(DMU_n/DBI-

U_n), (DML_n/

DBIL_n)

Input/

Output

Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data.

Input data is masked when DM_n is sampled LOW coincident with that input data during

a Write access. DM_n is sampled on both edges of DQS. DM is muxed with DBI function

by Mode Register A10,A11,A12 setting in MR5. For x8 device, the function of DM or

TDQS is enabled by Mode Register A11 setting in MR1. DBI_n is an input/output identif-

ing wherther to store/output the true or inverted data. If DBI_n is LOW, the data will be

stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH.

TDQS is only supported in x8.

BG0 - BG1

Input

Bank Group Inputs: BG0 - BG1 define to which bank group an Active, Read, Write or Pre-

charge command is being applied. BG0 also detemines which mode register is to be

accessed during a MRS cycle. x4/8 have BG0 and BG1 but x16 has only BG0.

BA0 - BA1

Input

Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Pre-

charge command is being applied. Bank address also determines if the mode register or

extended mode register is to be accessed during a MRS cycle.

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