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H5AN8G6NAFR-RDC Datasheet(PDF) 33 Page - Hynix Semiconductor |
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H5AN8G6NAFR-RDC Datasheet(HTML) 33 Page - Hynix Semiconductor |
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33 / 45 page ![]() Rev. 1.2 / Jul.2017 33 Input/Output Capacitance NOTE : 1. This parameter is not subject to production test. It is verified by design and characterization. The silicon only capacitance is vali- dated by de-embedding the package L & C parasitic. The capacitance is measured with VDD, VDDQ, VSS, VSSQ applied with all other signal pins floating. Measurement procedure tbd. 2. DQ, DM_n, DQS_T, DQS_C, TDQS_T, TDQS_C. Although the DM, TDQS_T and TDQS_C pins have different functions, the loading matches DQ and DQS 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value CK_T-CK_C 5. Absolute value of CIO(DQS_T)-CIO(DQS_C) 6. CI applies to ODT, CS_n, CKE, A0-A17, BA0-BA1, BG0-BG1, RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR. 7. CDI CTRL applies to ODT, CS_n and CKE 8. CDI_CTRL = CI(CTRL)-0.5*(CI(CLK_T)+CI(CLK_C)) 9. CDI_ADD_ CMD applies to, A0-A17, BA0-BA1, BG0-BG1,RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR. 10. CDI_ADD_CMD = CI(ADD_CMD)-0.5*(CI(CLK_T)+CI(CLK_C)) 11. CDIO = CIO(DQ,DM)-0.5*(CIO(DQS_T)+CIO(DQS_C)) 12. Maximum external load capacitance on ZQ pin: tbd pF. 13. TEN pis may be DRAM internally pulled low through a weak pull-down resistor to VSS. In this case CTEN might not be valid and system shall verify TEN signal with Vendor specific information. Silicon pad I/O Capacitance Symbol Parameter DDR4- 1600,1866,2133 DDR4-2400,2666 Unit NOTE min max min max CIO Input/output capacitance 0.55 1.4 0.55 1.15 pF 1,2,3 CDIO Input/output capacitance delta -0.1 0.1 -0.1 0.1 pF 1,2,3,11 CDDQS Input/output capacitance delta DQS_t and DQS_c 0.05 0.05 pF 1,2,3,5 CCK Input capacitance, CK_t and CK_c 0.2 0.8 0.2 0.7 pF 1,3 CDCK Input capacitance delta CK_t and CK_c 0.05 0.05 pF 1,3,4 CI Input capacitance (CTRL, ADD, CMD pins only) 0.2 0.8 0.2 0.7 pF 1,3,6 CDI_ CTRL Input capacitance delta (All CTRL pins only) -0.1 0.1 -0.1 0.1 pF 1,3,7,8 CDI_ ADD_CMD Input capacitance delta (All ADD/CMD pins only) -0.1 0.1 -0.1 0.1 pF 1,2,9,10 CALERT Input/output capacitance of ALERT 0.5 1.5 0.5 1.5 pF 1,3 CZQ Input/output capacitance of ZQ - 2.3 - 2.3 pF 1,3,12 CTEN Input capacitance of TEN 0.2 2.3 0.2 2.3 pF 1,3,13 |
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