H5AN8G6NAFR-RDC datasheet(40/45 Pages) HYNIX

40 / 45 page

Rev. 1.2 / Jul.2017

DDR4-2133 Speed Bins and Operations

Speed Bin

DDR4-2133P

Unit

NOTE

CL-nRCD-nRP

15-15-15

Parameter

Symbol

min

max

Internal read command to first data

tAA

14.0613

(13.50)5,11

18.00

Internal read command to first data

with read DBI enabled

tAA_DBI

tAA(min)+3nCK

tAA(max)+3nCK

ACT to internal read or write delay

time

tRCD

14.06

(13.50)5,11

PRE command period

tRP

14.06

(13.50)5,11

ACT to PRE command period

tRAS

9 x tREFI

ACT to ACT or REF command period

tRC

47.06

(46.50)5,11

Normal

Read DBI

CWL = 9

CL = 9

CL = 11

tCK(AVG)

1.5

1.6

1,2,3,4,10,

CL = 10

CL = 12

tCK(AVG)

Reserved

1,2,3,10

CWL = 9,11

CL = 11

CL = 13

tCK(AVG)

1.25

<1.5

1,2,3,4,7

CL = 12

CL = 14

tCK(AVG)

1.25

<1.5

1,2,3,7

CWL = 10,12

CL = 13

CL = 15

tCK(AVG)

1.071

<1.25

1,2,3,4,7

CL = 14

CL = 16

tCK(AVG)

1.071

<1.25

1,2,3,7

CWL = 11,14

CL = 14

CL = 17

tCK(AVG)

Reserved

1,2,3,4

CL = 15

CL = 18

tCK(AVG)

0.937

<1.071

1,2,3,4

CL = 16

CL = 19

tCK(AVG)

0.937

<1.071

1,2,3

Supported CL Settings

9,11,12,13,14,15,16

nCK

12,13

Supported CL Settings with read DBI

11,13,14,15,16,18,19

nCK

Supported CWL Settings

9,10,11,12,14

nCK

H5AN8G6NAFR-RDC Datasheet(PDF) 40 Page - Hynix Semiconductor

H5AN8G6NAFR-RDC Datasheet(HTML) 40 Page - Hynix Semiconductor

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