H5AN8G6NAFR-RDC datasheet(9/45 Pages) HYNIX

9 / 45 page

Rev. 1.2 / Jul.2017

A0 - A17

Input

Address Inputs: Provied the row address for ACTIVATE Commands and the column

address for Read/Write commands th select one location out of the memory array in the

respective bank. (A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have addi-

tional functions, see other rows. The address inputs also provide the op-code during

Mode Register Set commands. A17 is only defined for the x4 configration.

A10 / AP

Input

Auto-precharge: A10 is sampled during Read/Write commands to determine whether

Autoprecharge should be performed to the accessed bank after the Read/Write opera-

tion. (HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Pre-

charge command to determine whether the Precharge applies to one bank (A10 LOW) or

all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank

addresses.

A12 / BC_n

Input

Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if

burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped).

See command truth table for details.

RESET_n

Input

Active Low Asynchronous Reset: Reset is active whenRESET_n is LOW, and inactive

when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a

CMOS rail to rail signal with DC high and low at 80% and 20% of VDD.

Input /

Output

Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then

CRC code is added at the end of Data Burst. Any DQ from DQ0~DQ3 may indicate the

internal Vref level during test via Mode Register Setting MR4 A4=High. During this

mode, RTT value should be set to Hi-Z. Refer to vendor specific datasheets to determine

which DQ is used.

DQS_t, DQS_c,

DQSU_t, DQSU_c,

DQSL_t, DQSL_c

Input /

Output

Data Strobe: output with read data, input with write data. Edge-aligned with read data,

centered in write data. For x16, DQSL corresponds to the data on DQL0-DQL7; DQSU

corresponds to the data on DQU0-DQU7. The data strobe DQS_t, DQSL_t, and DQSU_t

are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively, to provide

differential pair signaling to the system during reads and writes. DDR4 SDRAM supports

differential data strobe only and does not support single-ended.

TDQS_t, TDQS_c Output

Termination Data Strobe: TDQS_t/TDQS_c is applicable for x8 DRAMs only. When

enabled via Mode Register A11 = 1 in MR1, the DRAM will enable the same termination

resistance function on TDQS_t/TDQS_c that is applied to DQS_t/DQS_c. When disabled

via mode register A11 = 0 in MR1, DM/DBI/TDQS will provide the data mask function or

Data Bus Inversion depending on MR5; A11, 12, 10 and TDQS_c is not used. x4/x16

DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.

PAR

Input

Command and Address Parity Input : DDR4 Supports Even Parity check in DRAM with

MR setting. Once it’s enabled via Register in MR5, then DRAM calculates Parity with

ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A17-A,0 and C0-

C2(3DS devices). Input parity should maintain at the rising edge of the clock and at the

same time with command & address with CS_n LOW.

ALERT_n

Output

Alert: It has multi functions such as CRC error flag, Command and Address Parity error

flag as Output signal. If there is error in CRC, then Alert_n goes LOW for the period time

interval and goes back HIGH. If there is error in Command Address Parity Check, then

Alert_n goes LOW for relatively long period until on going DRAM internal recovery trans-

action to complete. During Connectivity Test mode, this pin works as input. Using this

signal or not is dependent on system. In case of not connected as Signal, ALERT_n Pin

must be bounded to VDD on board.

Symbol

Type

Function

H5AN8G6NAFR-RDC Datasheet(PDF) 9 Page - Hynix Semiconductor

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