H5AN8G6NAFR-RDC datasheet(19/45 Pages) HYNIX

19 / 45 page

Rev. 1.2 / Jul.2017

IDD4W

Operating Burst Write Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: High between WR;

Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to

Table 8; Data IO: seamless write data burst with different data between one burst and the next one

according to Table 8; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through

banks: 0,0,1,1,2,2,... (see Table 8); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:

stable at HIGH; Pattern Details: see Table 8

IDD4WA

Operating Burst Write Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD4W

IDD4WB

Operating Burst Write Current with Write DBI

Write DBI enabled3, Other conditions: see IDD4W

IDD4WC

Operating Burst Write Current with Write CRC

Write CRC enabled3, Other conditions: see IDD4W

IDD4W_par

Operating Burst Write Current with CA Parity

CA Parity enabled3, Other conditions: see IDD4W

IPP4W

Operating Burst Write IPP Current

Same condition with IDD4W

IDD5B

Burst Refresh Current (1X REF)

CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 81; AL: 0; CS_n: High between REF;

Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to

Table 9; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: REF command every nRFC (see Table 9);

Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see

Table 9

IPP5B

Burst Refresh Write IPP Current (1X REF)

Same condition with IDD5B

IDD5F2

Burst Refresh Current (2X REF)

tRFC=tRFC_x2, Other conditions: see IDD5B

IPP5F2

Burst Refresh Write IPP Current (2X REF)

Same condition with IDD5F2

IDD5F4

Burst Refresh Current (4X REF)

tRFC=tRFC_x4, Other conditions: see IDD5B

IPP5F4

Burst Refresh Write IPP Current (4X REF)

Same condition with IDD5F4

IDD6N

Self Refresh Current: Normal Temperature Range

TCASE: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock:

Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group

Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation;

Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL

IPP6N

Self Refresh IPP Current: Normal Temperature Range

Same condition with IDD6N

IDD6E

Self-Refresh Current: Extended Temperature Range)

TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock:

Off; CK_t and CK_c: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n, Command, Address, Bank Group

Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature

Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL

IPP6E

Self Refresh IPP Current: Extended Temperature Range

Same condition with IDD6E

H5AN8G6NAFR-RDC Datasheet(PDF) 19 Page - Hynix Semiconductor

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