H5AN8G6NAFR-RDC datasheet(14/45 Pages) HYNIX

14 / 45 page

Rev. 1.2 / Jul.2017

IDD and IDDQ Specification Parameters and Test Conditions

IDD, IPP and IDDQ Measurement Conditions

In this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined.

Figure shows the setup and test load for IDD, IPP and IDDQ measurements.

•

IDD currents (such as IDD0, IDD0A, IDD1, IDD1A, IDD2N, IDD2NA, IDD2NL, IDD2NT, IDD2P, IDD2Q,

IDD3N, IDD3NA, IDD3P, IDD4R, IDD4RA, IDD4W, IDD4WA, IDD5B, IDD5F2, IDD5F4, IDD6N, IDD6E,

IDD6R, IDD6A, IDD7 and IDD8) are measured as time-averaged currents with all VDD balls of the

DDR4 SDRAM under test tied together. Any IPP or IDDQ current is not included in IDD currents.

•

IPP currents have the same definition as IDD except that the current on the VPP supply is measured.

•

IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all

VDDQ balls of the DDR4 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-

rents.



Attention: IDDQ values cannot be directly used to calculate IO power of the DDR4 SDRAM. They can

be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In

DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one

merged-power layer in Module PCB.

For IDD, IPP and IDDQ measurements, the following definitions apply:

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“0” and “LOW” is defined as VIN <= VILAC(max).

•

“1” and “HIGH” is defined as VIN >= VIHAC(min).

•

“MID-LEVEL” is defined as inputs are VREF = VDD / 2.

•

Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns are provided in Table 1.

•

Basic IDD, IPP and IDDQ Measurement Conditions are described in Table 2.

•

Detailed IDD, IPP and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 11.

•

IDD Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not lim-

ited to setting



RON = RZQ/7 (34 Ohm in MR1);



RTT_NOM = RZQ/6 (40 Ohm in MR1);



RTT_WR = RZQ/2 (120 Ohm in MR2);



RTT_PARK = Disable;



Qoff = 0B (Output Buffer enabled) in MR1;

TDQS_t disabled in MR1;



CRC disabled in MR2;



CA parity feature disabled in MR5;

Gear down mode disabled in MR3



Read/Write DBI disabled in MR5;



DM disabled in MR5

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Attention: The IDD, IPP and IDDQ Measurement-Loop Patterns need to be executed at least one time

before actual IDD or IDDQ measurement is started.

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Define D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, LOW, LOW, LOW, LOW} ; apply BG/BA

changes when directed.

•

Define D# = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, HIGH, HIGH, HIGH, HIGH} ; apply

invert of BG/BA changes when directed above.

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