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H5AN8G6NAFR-RDC Datasheet(PDF) 10 Page - Hynix Semiconductor |
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H5AN8G6NAFR-RDC Datasheet(HTML) 10 Page - Hynix Semiconductor |
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10 / 45 page ![]() Rev. 1.2 / Jul.2017 10 TEN Input Connectivity Test Mode Enable: Required on x16 devices and optional input on x4/x8 with densities equal to or greater than 8Gb. HIGH in this pin will enable Connectivity Test Mode operation along with other pins. It is a CMOS rail to rail signal with AC high and low at 80% and 20% of VDD. Using this signal or not is dependent on System. This pin may be DRAM internally pulled low through a weak pull-down resistor to VSS. NC No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.2 V +/- 0.06 V VSSQ Supply DQ Ground VDD Supply Power Supply: 1.2 V +/- 0.06 V VSS Supply Ground Vpp Supply DRAM Activation Power Supply: 2.5V (2.375V min , 2.75 max) VREFCA Supply Reference voltage for CA ZQ Supply Reference Pin for ZQ calibration Note: Input only pins (BG0-BG-1, BA0-BA1, A0-A17, ACT_n, RAS_n,/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and RESET_n) do not supply termination. Symbol Type Function |
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