H5AN8G6NAFR-RDC datasheet(39/45 Pages) HYNIX

39 / 45 page

Rev. 1.2 / Jul.2017

DDR4-1866 Speed Bins and Operations

Speed Bin

DDR4-1866M

Unit

NOTE

CL-nRCD-nRP

13-13-13

Parameter

Symbol

min

max

Internal read command to first

data

tAA

13.9213

(13.50)5,11

18.00

Internal read command to first

data with read DBI enabled

tAA_DBI

tAA(min) + 2nCK

tAA(max) +2nCK

ACT to internal read or write delay

time

tRCD

13.92

(13.50)5,11

PRE command period

tRP

13.92

(13.50)5,11

ACT to PRE command period

tRAS

9 x tREFI

ACT to ACT or REF command

period

tRC

47.92

(47.50)5,11

Normal Read DBI

CWL = 9

CL = 9

CL = 11 tCK(AVG)

1.5

1.6

1,2,3,4,10

,11

CL = 10

CL = 12 tCK(AVG)

Reserved

ns 1,2,3,4,10

CWL = 9,11

CL = 10

CL = 12 tCK(AVG)

Reserved

CL = 11

CL = 13 tCK(AVG)

1.25

<1.5

1,2,3,4,6

CL = 12

CL = 14 tCK(AVG)

1.25

<1.5

1,2,3,6

CWL = 10,12

CL = 12

CL = 14 tCK(AVG)

Reserved

1,2,3,4

CL = 13

CL = 15 tCK(AVG)

1.071

<1.25

1,2,3,4

CL = 14

CL = 16 tCK(AVG)

1.071

<1.25

1,2,3

Supported CL Settings

9,11,12,13,14

nCK

12,13

Supported CL Settings with read DBI

11,13,14 ,15,16

nCK

Supported CWL Settings

9,10,11,12

nCK

H5AN8G6NAFR-RDC Datasheet(PDF) 39 Page - Hynix Semiconductor

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