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H5AN8G6NAFR-RDC Datasheet(PDF) 4 Page - Hynix Semiconductor |
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H5AN8G6NAFR-RDC Datasheet(HTML) 4 Page - Hynix Semiconductor |
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4 / 45 page ![]() Rev. 1.2 / Jul.2017 4 ORDERING INFORMATION Part No. Configuration Package 96ball FBGA * xx means Speed Bin Grade OPERATING FREQUENCY MT/s Grade tCK (ns) CAS Latency (tCK) tRCD (ns) tRP (ns) tRAS (ns) tRC (ns) CL-tRCD-tRP *SK hynix DRAM devices support optional downbinning to CL17, CL15, CL13 and CL11. SPD setting is programmed to match. H5AN8G4NAFR-*xxc 2G x 4 78ball FBGA H5AN8G8NAFR-*xxC 1G x 8 H5AN8G6NAFR-*xxC 512M x 16 DDR4-1600 -PB 1.25 11 13.75 (13.50)* 13.75 (13.50)* 35 48.75 (48.50)* 11-11-11 DDR4-1866 -RD 1.071 13 13.92 (13.50)* 13.92 (13.50)* 34 47.92 (47.50)* 13-13-13 DDR4-2133 -TF 0.937 15 14.06 (13.50)* 14.06 (13.50)* 33 47.06 (46.50)* 15-15-15 DDR4-2400 -UH 0.833 17 14.16 (13.75)* 14.16 (13.75)* 32 46.16 (45.75)* 17-17-17 DDR4-2666 -VK 0.75 19 14.25 (13.75)* 14.25 (13.75)* 32 46.25 (45.75)* 19-19-19 |
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