H5AN8G6NAFR-RDC datasheet(17/45 Pages) HYNIX

17 / 45 page

Rev. 1.2 / Jul.2017

Table 2 -Basic IDD, IPP and IDDQ Measurement Conditions

Symbol

Description

IDD0

Operating One Bank Active-Precharge Current (AL=0)

CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 81; AL: 0; CS_n: High

between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially

toggling according to Table 3; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: Cycling with one

bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Regis-

ters2; ODT Signal: stable at 0; Pattern Details: see Table 3

IDD0A

Operating One Bank Active-Precharge Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD0

IPP0

Operating One Bank Active-Precharge IPP Current

Same condition with IDD0

IDD1

Operating One Bank Active-Read-Precharge Current (AL=0)

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 81; AL: 0; CS_n: High

between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs,

Data IO: partially toggling according to Table 4; DM_n: stable at 1; Bank Activity: Cycling with one

bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Regis-

ters2; ODT Signal: stable at 0; Pattern Details: see Table 4

IDD1A

Operating One Bank Active-Read-Precharge Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD1

IPP1

Operating One Bank Active-Read-Precharge IPP Current

Same condition with IDD1

IDD2N

Precharge Standby Current (AL=0)

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,

Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data

IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in

Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 5

IDD2NA

Precharge Standby Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD2N

IPP2N

Precharge Standby IPP Current

Same condition with IDD2N

IDD2NT

Precharge Standby ODT Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,

Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 6; Data

IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in

Mode Registers2; ODT Signal: toggling according to Table 6; Pattern Details: see Table 6

IDDQ2NT

(Optional)

Precharge Standby ODT IDDQ Current

Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current

IDD2NL

Precharge Standby Current with CAL enabled

Same definition like for IDD2N, CAL enabled3

IDD2NG

Precharge Standby Current with Gear Down mode enabled

Same definition like for IDD2N, Gear Down mode enabled3,5

IDD2ND

Precharge Standby Current with DLL disabled

Same definition like for IDD2N, DLL disabled3

H5AN8G6NAFR-RDC Datasheet(PDF) 17 Page - Hynix Semiconductor

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