H5AN8G6NAFR-RDC datasheet(43/45 Pages) HYNIX

43 / 45 page

Rev. 1.2 / Jul.2017

Speed Bin Table Notes

Absolute Specification

- VDDQ = VDD = 1.20V +/- 0.06 V

- VPP = 2.5V +0.25/-0.125 V

- The values defined with above-mentioned table are DLL ON case.

- DDR4-1600, 1866, 2133 and 2400 Speed Bin Tables are valid only when Geardown Mode is disabled.

1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making

a selection of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as require-

ments from CWL setting.

2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized

by the DLL - all possible intermediate frequencies may not be guaranteed. CL in clock cycle is calcu-

lated from tAA following rounding algorithm defined in DDR4 Device Operation(Rounding Algorithms)

3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg)

down to the next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071 ns or 0.938 ns or 0.833 ns). This result

is tCK(avg).MAX corresponding to CL SELECTED.

4. ‘Reserved’ settings are not allowed. User must program a different value.

5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a

mandatory feature. Refer to supplier's data sheet and/or the DIMM SPD information if and how this

setting is supported.

6. Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the

table which are not subject to Production Tests but verified by Design/Characterization.

7. Any DDR4-2133 speed bin also supports functional operation at lower frequencies as shown in the

table which are not subject to Production Tests but verified by Design/Characterization.

8. Any DDR4-2400 speed bin also supports functional operation at lower frequencies as shown in the

table which are not subject to Production Tests but verified by Design/Characterization.

9. Any DDR4-2666 speed bin also supports functional operation at lower frequencies as shown in the

table which are not subject to Production Tests but verified by Design/Characterization.

10. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.

11. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as

stated in the Speed Bin Tables.

12. CL number in parentheses, it means that these numbers are optional.

13. DDR4 SDRAM supports CL=9 as long as a system meets tAA(min).

14. Each speed bin lists the timing requirements that need to be supported in order for a given DRAM to

be JEDEC compliant. JEDEC compliance does not require support for all speed bins within a given

speed. JEDEC compliance requires meeting the parameters for a least one of the listed speed bins.

H5AN8G6NAFR-RDC Datasheet(PDF) 43 Page - Hynix Semiconductor