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SH79F166AP/044PR Datasheet(PDF) 45 Page - SINOWEALTH Electronic Ltd |
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SH79F166AP/044PR Datasheet(HTML) 45 Page - SINOWEALTH Electronic Ltd |
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45 / 113 page ![]() SH79F166A 45 7.8.3 Timer3 Timer3 is a 16-bit auto-reload timer. It is accessed as two cascaded Data Registers: TH3 and TL3. It is controlled by the T3CON register. The Timer3 interrupt can be enabled by setting ET3 bit in IEN1 register (Refer to Interrupt Section for details). Timer3 has only one operating mode: 16-bit Counter/Timer with auto-reload. Timer3 also supports the following features: selectable pre-scaler setting and Operation during CPU Power-Down mode. Timer3 consists of a 16-bit counter/reload register (TH3, TL3). When writing to TH3 and TL3, they are used as timer load register. When reading from TH3 and TL3, they are used as timer counter register. Setting the TR3 bit enables Timer 3 to count up. The Timer will overflow from 0xFFFF to 0x0000 and set the TF3 bit. This overflow also causes the 16-bit value written in timer load register to be reloaded into the timer counter register. Writing to TH3 also can cause the 16-bit value written in timer load register to be reloaded into the timer counter register. Read or write operation to TH3 and TL3 should follow these steps: Write operation: Low nibble first, High nibble to update the counter Read operation: High nibble first, Low nibble followed. TF3 The Block Diagram of Timer3 TL3 TH3 Increment Mode 0:Switch Off 1:Switch On 16-bit Counter Interrupt Request Overflow Flag TR3 System Clock Prescaler 1,8,64,256 T3PS[1:0] T3CLKS[1:0] 00 01 10 T3 32.768kHz Crystal Timer3 can operate even in Power-Down mode. When OP_OSC[3:0] (Refer to Code Option Section for details) is 1010, 1101, 0011 or 0110, T3CLKS [1:0] can select 00, 01 or 10. When OP_OSC[3:0] is not 1010, 1101, 0011 or 0110, T3CLKS[1:0] can select 00 or 01, and 10 will be an invalid value. If T3CLKS[1:0] is 00, Timer 3 can’t work in Power Down mode. If T3CLKS[1:0] is 01 and external clock input from T3 Pin, Timer3 can work in CPU normal operating or Power Down mode. If T3CLKS[1:0] is 10 and OP_OSC[3:0] is 1010, 1101, 0011 or 0110, Timer3 can work in CPU normal operating or Power Down mode (entering Power Down mode when system clock is high frequency). If T3CLKS[3:0] is 10 and OP_OSC[2:0] is not1010, 1101, 0011 or 0110, Timer3 can’t work. It can be described in the following table. OP_OSC[3:0] T3CLKS[1:0] Can work in normal mode Can work in Power Down mode 1010, 1101, 0011 or 0110 00 YES NO 01 YES YES 10 YES YES Not 1010, 1101, 0011 or 0110 00 YES NO 01 YES YES 10 NO NO Note: (1) When TH3 and TL3 read or written, must make sure TR3 = 0. (2) When T3 is selected as Timer3 clock source and TR3 is set 0 to 1, the first T3 down edge will be ignored. |
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