SH79F166APSLASH044PR datasheet(80/113 Pages) SINOWEALTH

80 / 113 page

SH79F166A

Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection of a falling

edge on the RxD pin. For this purpose RxD is sampled at the rate of 16 times baud rate. When a falling edge is detected, the

divide-by-16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of the divide-by-16 counter.

The 16 states of the counter divide each bit time into 16ths. The bit detector samples the value of RxD at the 7

th, 8th and 9th

counter state of each bit time. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for

noise rejection. If the first bit detected after the falling edge of RxD pin is not 0, which indicates an invalid start bit, and the

reception is immediately aborted. The receive circuits are reset and again looks for a falling edge in the RxD line. If a valid start

bit is detected, then the rest of the bits are also detected and shifted into the shift register. After shifting in 9 data bits and the

stop bit, the SBUF and RB8 are loaded and RI is set if the following conditions are met:

1. RI must be 0

2. Either SM2 = 0, or the received 9

th bit = 1 and the received byte accords with Given Address

If these conditions are met, then the 9

th bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise the received

frame may be lost.

At the time, the receiver goes back to looking for another falling edge on the RxD pin. And the user should clear RI by software

for further reception.

Shift CLK

RxD

Bit Sample

Start

Stop

Receive Timing of Mode 2

Mode3: 9-Bit EUART, Variable Baud Rate, Asynchronous Full-Duplex

Mode3 uses transmission protocol of the Mode2 and baud rate generation of the Mode1.

Timer 4 Overflow

SERIAL

CONTROLLER

TX CLOCK

TX START

TX SHIFT

RX CLOCK

LOAD SBUF

RX START

RX SHIFT

Serial Port Interrupt

CLOCK

SIN

PAROUT

RXD

Read SBUF

Internal

Data Bus

Receive Shift Register

Timer 2 Overflow

1-TO-0

DETECTOR

Write to SBUF

BIT

DETECTOR

SBUF

RB8

SAMPLE

TXD

PARIN

LOAD

CLOCK

SOUT

Internal

Data Bus

Transmit Shift Register

START

TB8

STOP

TCLK

RCLK

SH79F166AP/044PR Datasheet(PDF) 80 Page - SINOWEALTH Electronic Ltd

SH79F166AP/044PR Datasheet(HTML) 80 Page - SINOWEALTH Electronic Ltd

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