SH79F166APSLASH044PR datasheet(55/113 Pages) SINOWEALTH

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SH79F166A

7.9.3 Interrupt Flag

Each Interrupt source has its own interrupt flag, when interrupt occurs, corresponding flag will be set by hardware, the interrupt

flag bits are listed in Table bellow.

For external interrupt (INT0/1/2/3), when an external interrupt0/1/2/3 is generated, if the interrupt was edge trigged, the flag

(IE0-3 in TCON) that generated this interrupt is cleared by hardware when the service routine is vectored. If the interrupt was

level trigged, then the requesting external source directly controls the request flag, rather than the on-chip hardware.

When an external interrupt4 is generated, the flag (IF4x (x = 0-3) in EXF1 register) that generated this interrupt should be

cleared by user’s program because the same vector entrance was used in INT4. But if INT4 is setup as level trigged, the flag

can’t be cleared by user’s program, it only be controlled by peripheral signal level that connect to INT source pin.

The timer 2 interrupt is generated by the logical OR of flag TF2 and bit EXF2 in T2CON register, which is set by hardware.

None of these flags can be cleared by hardware when the service routine is vectored. In fact, the service routine may have to

determine whether it was TF2 or EXF2 that generated the interrupt, so the flag must be cleared by software.

The timer 3 interrupt is generated when they overflow, the flag TF3 in T3CON register, which is set by hardware, and will be

automatically cleared by hardware when the service routine is vectored.

The timer 4 interrupt is generated when they overflow, the flag TF4 in T4CON register, which is set by hardware, and will be

automatically cleared by hardware when the service routine is vectored.

The timer 5 interrupt is generated when they overflow, the flag TF5 in T4CON register, which is set by hardware, and will be

automatically cleared by hardware when the service routine is vectored.

The EUART interrupt is generated by the logical OR of flag RI and TI in SCON register, which is set by hardware. Neither of

these flags can be cleared by hardware when the service routine is vectored. In fact, the service routine will normally have to

determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt, so the flag

must be cleared by software.

The ADC interrupt is generated by ADCIF bit in ADCON. If an interrupt is generated, the converted result in ADCDH/ADCDL

will be valid. If continuous compare function in ADC module is Enable, ADCIF will not be set at each conversion, but set if

converted result is larger than compare value. The flag must be cleared by software.

The SCM interrupt is generated by SCMIF in SCM register, which is set by hardware. And the flag can only be cleared by

hardware.

The LPD interrupt is generated by LPDF in LPDCON register. And the flag can only be cleared by hardware.

The PWM interrupts are generated by PWM0IF in PWM0C. The flags can be cleared by software.

Table 7.41 Enternal Interrupt Flag Register

88H, Bank0

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

TCON

IE1

IT1

IE0

IT0

R/W

Reset Value

(POR/WDT/LVR/PIN)

Bit Number

Bit Mnemonic

Description

1, 3

IEx

(x = 0, 1)

External interrupt x request flag bit

0: No interrupt pending

1: Interrupt is pending

0, 2

ITx

(x = 0, 1)

External interrupt x trigger mode selection bit

0: Low level trigger

1: Falling edge trigger

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