SH79F166APSLASH044PR datasheet(78/113 Pages) SINOWEALTH

78 / 113 page

SH79F166A

Transmission begins with a “write to SBUF” signal, and it actually commences at the next system clock following the next

rollover in the divide-by-16 counter (divide baud-rate by 16), thus, the bit times are synchronized to the divide-by-16 counter,

not to the “write to SUBF” signal. The start bit is firstly put out on TxD pin, then are the 8 bits of data. After all 8 bits of data in the

transmit shift register are transmitted, the stop bit is put out on the TxD pin, and the TI flag is set at the same time that the stop

is send.

Write to SBUF

Shift CLK

TxD

Stop

Start

Send Timing of Mode 1

Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data with the detection of a falling

edge on the RxD pin. For this purpose RxD is sampled at the rate of 16 times baud rate. When a falling edge is detected, the

divide-by-16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of the divide-by-16

counter.The 16 states of the counter divide each bit time into 16ths. The bit detector samples the value of RxD at the 7

th, 8th and

th counter states of each bit time. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for

noise rejection. If the first bit after the falling edge of RxD pin is not 0, which indicates an invalid start bit, and the reception is

immediately aborted. The receive circuits are reset and again waiting for a falling edge in the RxD line. If a valid start bit is

detected, then the rest of the bits are also detected and shifted into the shift register. After shifting in 8 data bits and the stop bit,

the SBUF and RB8 are loaded and RI are set if the following conditions are met:

1. RI must be 0

2. Either SM2 = 0, or the received stop bit = 1

If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise the received

frame may be lost.

At the time, the receiver goes back to looking for another falling edge on the RxD pin. And the user should clear RI by software

for further reception.

Receive Timing of Mode 1

RxD

Stop

Start

Bit Sample

Shift CLK

SH79F166AP/044PR Datasheet(PDF) 78 Page - SINOWEALTH Electronic Ltd