SH79F166APSLASH044PR datasheet(58/113 Pages) SINOWEALTH

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SH79F166A

7.9.6 Interrupt Handling

The interrupt flags are sampled and polled at the fetch cycle of each machine cycle. All interrupts are sampled at the rising edge

of the clock. If one of the flags was set, the CPU will find it and the interrupt system will generate a LCALL to the appropriate

service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions:

An interrupt of equal or higher priority is already in progress.

The current cycle is not in the final cycle of the instruction in progress. This ensures that the instruction in progress is completed

before vectoring to any service routine.

The instruction in progress is RETI. This ensures that if the instruction in progress is RETI then at least one more instruction

except RETI will be executed before any interrupt is vectored to; this delay guarantees that the CPU can observe the changes

of the interrupt status.

Note:

Since priority change normally needs 2 instructions, it is recommended to disable corresponding Interrupt Enable flag to avoid

interrupt between these 2 instructions during the change of priority.

If the flag is no longer active when the blocking condition is removed, the denied interrupt will not be serviced. Every polling

cycle interrogates only the valid interrupt requests.

The polling cycle/LCALL sequence is illustrated below:

Interrupt

Latched

Interrupt

Polled

Long Call to

Interrupt Vector Service

Interrupt

service

Cn+8

Interrupt

Pending

Interrupt

Signal

Generated

C3~Cn

Cn~Cn+7

Interrupt Response Timing

The hardware-generated LCALL pushes the contents of the program counter onto the stack (but it does not save the PSW) and

reloads the program counter with corresponding address that depends on the source of the interrupt being vectored too, as

shown in Interrupt Summary table.

Interrupt service execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs

the processor that the interrupt routine is no longer in progress, and then pops the top two bytes from the stack and reloads the

program counter. Execution of the interrupted program continues from the point where it was stopped. Note that the RETI

instruction is very important because it informs the processor that the program left the current interrupt service. A simple RET

instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system

thinking an interrupt with this priority was still in progress. In this case, no interrupt of the same or lower priority level would be

acknowledged.

7.9.7 Interrupt Response Time

If an interrupt is recognized, its request flag is set in every machine cycle after recognize. The value will be polled by the circuitry

until the next machine cycle; the CPU will generate an interrupt at the third machine cycle. If the request is active and conditions

are right for it to be acknowledged, hardware LCALL to the requested service routine will be the next instruction to be executed.

Else the interrupt will pending. The call itself takes 7 machine cycles. Thus a minimum of 3+7 complete machine cycles will

elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service

routine.

A longer response time would be obtained if the request was blocked by one of the above three previously listed conditions. If

an interrupt of equal or higher priority is already in progress, the additional wait time obviously depends on the nature of the

other interrupt’s service routine.

If the instruction in progress is not in its final cycle and the instruction in progress is RETI，the additional wait time is 8 machine

cycles. For a single interrupt system, if the next instruction is 20 machine cycles long (the longest instructions DIV & MUL are 20

machine cycles long for 16 bit operation), adding the LCALL instruction 7 machine cycles the total response time is 2+8+20+7

machine cycles.

Thus interrupt response time is always more than 10 machine cycles and less than 37 machine cycles.

SH79F166AP/044PR Datasheet(PDF) 58 Page - SINOWEALTH Electronic Ltd

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