SH79F166APSLASH044PR datasheet(82/113 Pages) SINOWEALTH

82 / 113 page

SH79F166A

Slave 1

Slave 2

SADDR

10100100

10100111

SADEN (0 mask)

11111010

11111001

Given Address

10100x0x

10100xx1

Broadcast Address (OR)

1111111x

11111111

The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don’t care, while for slave 2 it is 1. Thus to communicate

only with slave 1, the master must send an address with LSB = 0 (10100000). Similarly the bit 1 is 0 for slave 1 and don’t care

for slave 2. Hence to communicate only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the

master wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit 1 = 0. The bit 2

position is don’t care for both the slaves. This allows two different addresses to select both slaves (1010 0001 and 1010 0101).

The master can communicate with all the slaves simultaneously with the Broadcast Address. This address is formed from the

logical OR of the SADDR and SADEN. The zeros in the result are defined as don’t cares. In most cases, the Broadcast Address

is FFh, this address will be acknowledged by all slaves.

On reset, the SADDR and SADEN are initialized to 00h. This results in Given Address and Broadcast Address being set as

XXXXXXXX (all bits don’t care). This effectively removes the multiprocessor communications feature, since any selectivity is

disabled. This ensures that the EUART 0 will reply to any address, which it is backwards compatible with the 80C51

microcontrollers that do not support automatic address recognition. So the user may implement multiprocessor by software

address recognition mentioned above.

8.4.5 Error Detection

Error detection is available when the SSTAT bit in register PCON is set to logic 1.The SSTAT bit must be logic 1 to access any

of the status bits (FE, RXOV, and TXCOL). The SSTAT bit must be logic 0 to access the Mode Select bits (SM0, SM1, and

SM2).All the 3 bits should be cleared by software after they are set, even when the following frames received without any error

will not be cleared automatically.

Transmit Collision

The Transmit Collision bit (TXCOL bit in register SCON) reads ‘1’ if RI is set 0 and user software writes data to the SBUF

register while a transmission is still in progress. If this occurs, the new data will be ignored and the transmit buffer will not be

written.

Receive Overrun

The Receive Overrun bit (RXOV in register SCON) reads ‘1’ if a new data byte is latched into the receive buffer before software

has read the previous byte. The previous data is lost when this happen.

Frame Error

The Frame Error bit (FE in register SCON) reads ‘1’ if an invalid (low) STOP bit is detected.

Break Detection

A break is detected when any 11 consecutive bits are sensed low. Since a break condition also satisfies the requirements for a

framing error, a break condition will also result in reporting a framing error. Once a break condition has been detected, the

EUART will go into an idle state and remain in this idle state until a valid stop bit (rising edge on RxD line) has been received.

SH79F166AP/044PR Datasheet(PDF) 82 Page - SINOWEALTH Electronic Ltd

SH79F166AP/044PR Datasheet(HTML) 82 Page - SINOWEALTH Electronic Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL