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SH79F166AP/044PR Datasheet(PDF) 83 Page - SINOWEALTH Electronic Ltd |
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SH79F166AP/044PR Datasheet(HTML) 83 Page - SINOWEALTH Electronic Ltd |
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83 / 113 page  SH79F166A 83 8.4.6 Register Table 8.21 EUART Control & Status Register 98H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCON SM0 /FE SM1 /RXOV SM2 /TXCOL REN TB8 RB8 TI RI R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-6 SM[0:1] EUART Serial mode control bit, when SSTAT = 0 00: mode 0, Synchronous Mode, fixed baud rate 01: mode 1, 8 bit Asynchronous Mode, variable baud rate 10: mode 2, 9 bit Asynchronous Mode, fixed baud rate 11: mode 3, 9 bit Asynchronous Mode, variable baud rate 7 FE EUART Frame Error flag, when FE bit is read, SSTAT bit must be set 1 0: No Frame Error, clear by software 1: Frame error occurs, set by hardware 6 RXOV EUART Receive Over flag, when RXOV bit is read, SSTAT bit must be set 1 0: No Receive Over, clear by software 1: Receive over occurs, set by hardware 5 SM2 EUART Multi-processor communication enable bit (9 th bit ‘1’ checker), when SSTAT = 0 0: In Mode0, baud-rate is 1/12 of system clock In Mode1, disable stop bit validation check, any stop bit will set RI to generate interrupt In Mode2 & 3, any byte will set RI to generate interrupt 1: In Mode0, baud-rate is 1/4 of system clock In Mode1, Enable stop bit validation check, only valid stop bit (1) will set RI to generate interrupt In Mode2 & 3, only address byte (9 th bit = 1) will set RI to generate interrupt 5 TXCOL EUART Transmit Collision flag, when TXCOL bit is read, SSTAT bit must be set 1 0: No Transmit Collision, clear by software 1: Transmit Collision occurs, set by hardware 4 REN EUART Receiver enable bit 0: Receive Disable 1: Receive Enable 3 TB8 The 9th bit to be transmitted in Mode2 & 3 of EUART, set or clear by software 2 RB8 The 9th bit to be received in Mode1, 2 & 3 of EUART In Mode0, RB8 is not used In Mode1, if receive interrupt occurs, RB8 is the stop bit that was received In Modes2 & 3 it is the 9 th bit that was received 1 TI Transmit interrupt flag of EUART 0: cleared by software 1: Set by hardware at the end of the 8 th bit time in Mode0, or at the beginning of the stop bit in other modes 0 RI Receive interrupt flag of EUART 0: cleared by software 1: Set by hardware at the end of the 8 th bit time in Mode0, or during the stop bit time in other modes |
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