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SH79F166AP/044PR Datasheet(PDF) 94 Page - SINOWEALTH Electronic Ltd |
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SH79F166AP/044PR Datasheet(HTML) 94 Page - SINOWEALTH Electronic Ltd |
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94 / 113 page  SH79F166A 94 8.9.2 Register Table 8.32 Reset Control Register B1H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RSTSTAT WDOF - PORF LVRF CLRF WDT.2 WDT.1 WDT.0 R/W R/W - R/W R/W R/W R/W R/W R/W Reset Value (POR) 0 - 1 0 0 0 0 0 Reset Value (WDT) 1 - u u u 0 0 0 Reset Value (LVR) u - u 1 u 0 0 0 Reset Value (PIN) u - u u 1 0 0 0 Bit Number Bit Mnemonic Description 7 WDOF Watch Dog Timer Overflow or OVL Reset Flag Set by hardware when WDT overflow or OVL reset happened, cleared by software or Power On Reset 0: Watch Dog not overflows and no OVL reset generated 1: Watch Dog overflow or OVL reset occurred 5 PORF Power On Reset Flag Set only by Power On Reset, cleared only by software 0: No Power On Reset. 1: Power On Reset occurred. 4 LVRF Low Voltage Reset Flag Set only by Low Voltage Reset, cleared by software or Power On Reset 0: No Low Voltage Reset occurs 1: Low Voltage Reset occurred 3 CLRF Pin Reset Flag Set only by pin reset, cleared by software or Power On Reset 0: No Pin Reset occurs 1: Pin Reset occurred 2-0 WDT[2:0] WDT Overflow period control bit 000: Overflow period minimal value= 4096 ms 001: Overflow period minimal value= 1024 ms 010: Overflow period minimal value = 256 ms 011: Overflow period minimal value = 128 ms 100: Overflow period minimal value = 64ms 101: Overflow period minimal value = 16ms 110: Overflow period minimal value = 4ms 111: Overflow period minimal value = 1ms Notes: If WDT_opt is enable in application, you must clear WatchDog periodically, and the interval must be less than the value list above. |
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