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FS32R274VCK2MMM Datasheet(PDF) 27 Page - NXP Semiconductors

Part # FS32R274VCK2MMM
Description  S32R274/S32R264 Series Data Sheet
PDF  78 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS32R274VCK2MMM Datasheet(HTML) 27 Page - NXP Semiconductors

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IRCOSC
XOSC
PLL_0
PLL_1
PLL_0_PHI0
PLL_0_PHI1
PLL_1_PHI0
Figure 6. PLL integration
Table 20. PLL0 electrical characteristics
Symbol
Parameter
Conditions1
Min
Typ
Max
Unit
fPLL0IN
PLL0 input clock2, 3
—
14
—
44
MHz
PLL0IN
PLL0 input clock duty cycle2
—
40
—
60
%
fPLL0VCO
PLL0 VCO frequency
—
600
—
1250
MHz
fPLL0PHI0
PLL0 output clock PHI0
—
4.76
—
6254
MHz
fPLL0PHI1
PLL0 output clock PHI1
—
20
—
156
MHz
tPLL0LOCK
PLL0 lock time
—
—
—
100
µs
PLL0LTJ
PLL0 long term jitter fPLL0IN = 8 MHz
(resonator)5
fPLL0PHI0 = 40 MHz, 1 μs
± 1
ns
fPLL0PHI0 = 40 MHz, 13 μs
± 1
ns
IPLL0
PLL0 consumption
—
—
5
mA
1. VDD_LV_PLL0 =1.25 V ± 5%, TJ = -40 / 150 °C unless otherwise specified.
2. PLL0IN clock retrieved directly from either IRCOSC or external XOSC clock.
3. fPLL0IN frequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure the reference clock to the PLL analog
loop is in the range 8 MHz-20 MHz
4. The maximum clock outputs are limited by the design clock frequency requirements as per recommended operating
conditions.
5. VDD_LV_PLL0 noise due to application in the range VDD_LV_PLL0 = 1.25 V±5%, with frequency below PLL bandwidth (40 KHz)
will be filtered.
Table 21. FMPLL1 electrical characteristics
Symbol
Parameter
Conditions1
Min
Typ
Max
Unit
fPLL1IN
PLL1 input clock2
—
38
—
78
MHz
PLL1IN
PLL1 input clock duty cycle2
—
35
—
65
%
fPLL1VCO
PLL1 VCO frequency
—
600
—
1250
MHz
fPLL1PHI0
PLL1 output clock PHI0
—
4.76
—
625
MHz
tPLL1LOCK
PLL1 lock time
—
—
—
100
µs
fPLL1MOD
PLL1 modulation frequency
—
—
—
250
kHz
|
δPLL1MOD|
PLL1 modulation depth (when
enabled)
Center spread
0.25
—
2
%
Down spread
0.5
—
4
%
IPLL1
PLL1 consumption
—
—
6
mA
1. VDD_LV_PLL0 = 1.25 V ± 5%, TJ = -40 / 150°C unless otherwise specified.
2. PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock.
Clocks and PLL Specifications
S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021
NXP Semiconductors
27



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