FS32R274VCK2MMM datasheet(75/78 Pages) NXP

75 / 78 page

PHASE1,2

PHASE3

DRUN

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

Application

Flash

Init

Device

TFRL, min < TRESET < TFRL, max

execution

config

Figure 45. Functional reset sequence long

PHASE3

DRUN

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

Application

Execution

TFRS, min < TRESET < TFRS, max

Figure 46. Functional reset sequence short

The reset sequences shown in Figure 45 and Figure 46 are triggered by functional reset

events. RESET is driven low during these two reset sequences only if the corresponding

functional reset source (which triggered the reset sequence) was enabled to drive

RESET_B low for the duration of the internal reset sequence. See the RGM_FBRE

18 Power sequencing requirements

The device does not require any specific power sequencing as far as user follows

recommendations in this section.

Either ramp VDD_HV_IO and VDD_HV_PMU together or ramp V DD_HV_IO before

VDD_HV_PMU such that the two supplies always maintain 100 mV or less difference, when

using internal regulation mode. VDD_LV_DPHY and VDD_LV_CORE are to be driven from

same source. VDD_HV_IO, VDD_HV_IO_RGMII, VDD_HV_IO_PWM and VDD_HV_IO_LFAST

supplies should be treated as a single supply from board perspective.

As mentioned in the previous section, it is expected that the external ASIC which powers

up the device in external regulation mode deasserts VREG_POR_B pin only when all the

power supplies to the design are in operating range.

Power sequencing requirements

S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

NXP Semiconductors

FS32R274VCK2MMM Datasheet(PDF) 75 Page - NXP Semiconductors