FS32R274VCK2MMM datasheet(58/78 Pages) NXP

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9.5 LINFlexD timing specifications

The maximum bit rate is 1.875 MBit/s.

9.6 I2C timing

Table 44. I2C SCL and SDA input timing specifications

Number

Symbol

Parameter

Value

Unit

Min

Max

I_tHD:STA

Start Condition hold time

Peripheral clock

I_t_LOW

Clock low time

I_tHD:DAT

Data hold time

I_tHIGH

Clock high time

I_tSU:DAT

Data setup time

I_tSU:STA

Start condition setup time (for repeated

start condition only)

I_tSU:STOP

Stop condition setup time

Table 45. I2C SCL and SDA output timing specifications

Number

Symbol

Parameter

Value

Unit

Min

Max

O_tHD:STA

Start condition hold time1

Peripheral clock

O_t_LOW

Clock low time1

O_tHD:DAT

Data hold time1

O_t_HIGH

Clock high time1

O_tSU:DAT

Data setup time1

O_tSU:STA

Start condition setup time (for

repeated start condition only)1

O_tSU:STOP

Stop condition setup time1

O_tr

SCL/SDA rise time2

99.6

O_tf

SCL/SDA fall time1

99.6

1. Programming IBFD (I2C Bus Frequency Divider Register) with the maximum frequency results in the minimum output

timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.

The actual position is affected by the prescale and division values programmed in IBDR (I2C Bus Data I/O Register).

2. Serial data (SDA) and Serial clock (SCL) reaches peak level depending upon the external signal capacitance and pull up

resistor values as SDA and SCL are open-drain type outputs which are only actively driven low by the I2C module.

Communication modules

S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

NXP Semiconductors

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