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FS32R274VCK2MMM Datasheet(PDF) 74 Page - NXP Semiconductors |
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FS32R274VCK2MMM Datasheet(HTML) 74 Page - NXP Semiconductors |
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74 / 78 page ![]() be generated by an external pullup resistor which is strong enough to overdrive the weak internal pulldown resistor. The rising edge on RESET_B in the following figures indicates the time when the device stops driving it low. The reset sequence durations given in Table 57 are applicable only if the internal reset sequence is not prolonged by an external reset generator keeping RESET_B asserted low beyond the last Phase3. PHASE0 PHASE1,2 PHASE3 PHASE1,2 PHASE3 DRUN BIST Reset Sequence Trigger Reset Sequence Start Condition RESET_B Establish Flash Device Self MBIST LBIST Application IRC and PWR Init Test Setup Config Flash Init Device TDRB, min < TRESET < TDRB, max execution config Figure 42. Destructive reset sequence, BIST enabled PHASE0 PHASE1,2 PHASE3 DRUN Reset Sequence Trigger Reset Sequence Start Condition RESET_B Establish Flash Device Application IRC and PWR Init Config Execution TDR, min < TRESET < TDR, max Figure 43. Destructive reset sequence, BIST disabled PHASE1,2 PHASE3 PHASE1,2 PHASE3 DRUN BIST Reset Sequence Trigger Reset Sequence Start Condition RESET_B Flash Device Self MBIST LBIST Application Init Test Setup Config Flash Init Device TERLB, min < TRESET < TERLB, max execution config Figure 44. External reset sequence long, BIST enabled Reset sequence S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021 74 NXP Semiconductors |
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