FS32R274VCK2MMM datasheet(42/78 Pages) NXP

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MII7

MII8

Valid data

MII6

MII5

TXCLK (input)

TXD[n:0]

TXEN

TXER

Figure 10. MII transmit signal timing diagram

MII2

MII1

MII4

MII3

Valid data

RXCLK (input)

RXD[n:0]

RXDV

RXER

Figure 11. MII receive signal timing diagram

9.1.2 RMII signal switching specifications

The following timing specs meet the requirements for RMII style interfaces for a range of

transceiver devices.

• Measurements are with input transition of 1 ns and output load of 25 pF.

Table 34. RMII signal switching specifications

Num

Description

Min.

Max.

Unit

—

EXTAL frequency (RMII input clock RMII_CLK)

—

MHz

RMII1

RMII_CLK pulse width high

35%

65%

RMII_CLK

period

RMII2

RMII_CLK pulse width low

35%

65%

RMII_CLK

period

RMII3

RXD[1:0], CRS_DV, RXER to RMII_CLK setup

—

RMII4

RMII_CLK to RXD[1:0], CRS_DV, RXER hold

—

RMII7

RMII_CLK to TXD[1:0], TXEN invalid

—

Table continues on the next page...

Communication modules

S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

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