FS32R274VCK2MMM datasheet(29/78 Pages) NXP

29 / 78 page

Table 24. LFAST PLL electrical characteristics

(continued)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Long term, fRF_REF = 10

MHz

–500

—

500

ΔPEREYE

Output Eye Jitter (peak to peak)3

Random Jitter (Rj)

—

101

Deterministic Jitter (Dj)

—

Total Jitter @BER 10-9

—

1.09

1.31

bits

per

second

IVDD_LV_LFASTPLL

VDD_LV_LFASTPLL Supply Current

Normal Mode

—

Peak

—

Power Down

—

0.5

μA

1. The 640 MHz frequency is achieved with a 10 MHz or 20 MHz reference clock. With a 26 MHz reference, the VCO

frequency is 624 MHz.

2. The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral

bridge clock that is connected to the PLL on the device.

3. Measured at the transmitter output across a 100 Ω termination resistor on a device evaluation board.

Analog modules

7.1 ADC electrical characteristics

The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-

Digital Converter.

Analog modules

S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

NXP Semiconductors

FS32R274VCK2MMM Datasheet(PDF) 29 Page - NXP Semiconductors

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