CIRCC datasheet(23/70 Pages) SMSC

23 / 70 page

SCE CONTROLS

The CIrCC SCE Registers are arranged in 7-byte

blocks. Of the eight possible register blocks, four

are used in this implementation.

The Master Block Control Register controls

access to the register blocks. Table 13 lists all of

the SCE registers in all blocks.

Table 13 - SCE Register Addressing

BLOCK

ADDRESS

DIRECTION

R/W

Master Block Control

R/W

Data Register

Interrupt Identification

R/W

Interrupt Enable

Line Status (read)

Line Status Address (write)

R/W

Line Control A

R/W

Line Control B

R/W

Bus Status

R/W

SCE Configuration A

R/W

SCE Configuration B

R/W

FIFO Threshold

FIFO COUNT

R/W

SCE Configuration C

R/W

Consumer IR Control

R/W

Consumer IR Carrier Rate

R/W

Consumer IR Bit Rate

R/W

Custom Code

R/W

Custom Code

R/W

Data Code

SMSC ID (high)

SMSC ID (low)

CHIP ID

VERSION Number

IRQ Level

DMA Channel

Software Select A

Software Select B

CIRCC Datasheet(PDF) 23 Page - SMSC Corporation

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