CIRCC datasheet(35/70 Pages) SMSC

35 / 70 page

(Remote Control) encoder/decoder configuration

registers (Table 23).

Table 23 - Register Block Two

ADDRESS

DIR

DESCRIPTION

DEFAULT

R/W

Consumer IR Remote Control Register

'00'hex

sync

bit

frame

pme

wake

nccc

ncdc

carrier

off

carrier

range bits

R/W

Consumer IR Carrier Rate Register

'29'hex

R/W

Consumer IR Bit Rate Register

'37'hex

R/W

Custom Code

'00'hex

R/W

Custom Code’

'00'hex

R/W

Data Code

'00'hex

Reserved

Consumer IR Control Register (Address 0)

Sync Bit, bit 7

The Sync Bit enables the receiver bit-rate clock

synchronization mechanism. When the Sync bit

is one, receiver edge synchronization is enabled

(see the Receiver Bit Cell Synchronization

section on page 16).

Frame Bit, bit 6

The Frame bit determines the compatibility mode

of the CIR decoder (Table 24). If the Frame bit is

one, the CIR hardware decodes NEC PPM

remote control frames. If the Frame bit is zero

(default), frame decoding must be performed in

software.

PME Wake, bit 5

The PME Wake bit is used to configure the CIR

decoder for a PME wake-up event and to clear

the PME output (Table 24).

When the PME

Wake bit is one, the CIR decoder qualifies

incoming message frames depending upon the

state of the 16 bit Custom Code register, the 8 bit

Data Code register, the NCCC bit and the NCDC

bit and activates the CIrCC PME output when

appropriate. When the PME Wake bit is one, the

data received from NEC CIR remote frames is

not sent to the FIFO. When the PME Wake bit is

zero (default), the CIrCC PME output is cleared,

the CIR decoder qualifies incoming message

frames depending on the state of the 16 bit

Custom Code register and the NCCC bit, and

sends valid data to the FIFO.

NCCC, bit 4

The

Care

Custom

Code

(NCCC)

bit

determines the behavior of the CIR decoder

when the Frame bit is active (one) (Table 24).

When the NCCC bit is one and the PME Wake

bit is one, a PME event will be generated upon

receipt of a valid NEC CIR frame if the data code

field of the NEC frame matches the value of the

Data Code register, regardless of the custom

code field of the incoming frame. When the

NCCC bit is zero (default) and the PME Wake bit

is active (one), a PME event may be generated if

the custom code of the incoming NEC CIR frame

matches the value programmed into the 16 bit

Custom Code register, depending upon NCDC

qualification. When the NCCC bit is one and the

PME Wake bit is inactive (zero), the 8 bit data

code and the 16 bit custom code field of any

valid NEC CIR frame that is received will be sent

to the FIFO.

When the NCCC bit is zero

(default) and the PME Wake bit is zero, the data

code field of an incoming NEC CIR frame will be

written to the FIFO if the custom code field

matches the value programmed into the 16 bit

Custom Code register.

Non-qualifying frames

are ignored by the hardware.

NCDC, bit 3

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