CIRCC datasheet(28/70 Pages) SMSC

28 / 70 page

Line Control Register B (Address 5)

SCE Modes, bits 6 - 7

The SCE Modes bits enable the SCE transmitter

and receiver (Table 16). These bits are R/W and

must be manually reset by the host following CIR

message transactions when the FRAME bit is

one.

The SCE Modes bits are automatically

reset by the hardware following FIFO Overruns

or Underruns. Note: The SCE Modes bits must

be zero for loopback tests.

Table 16 - SCE Modes

MODE DESCRIPTION

Receive/Transmit Disabled (default)

Transmit Mode

Receive Mode

Undefined

Transmit Mode

Transmit mode enables the SCE Consumer IR

transmitter whenever TC goes active, or the

FIFO THRESHOLD has been exceeded (see the

Transmit Timing section on page 54).

Transmit

mode,

the

SCE

FIFO

input

connected to the Host System Data Bus and the

FIFO output is connected to the SCE transmitter

input. The Consumer IR encoder will reset

Transmit mode in hardware following the rising

edge

nActive

Frame

following

FIFO

underrun.

Receive Mode

Receive mode enables the SCE Consumer IR

receiver (see the Receive Timing section on

page 54).

In Receive mode, the SCE FIFO

output is connected to the Host System Data

Bus, the FIFO input is connected to the SCE

receiver output. The Consumer IR encoder will

reset Receive mode in hardware following the

rising edge of nActive Frame following a FIFO

underrun or TC.

CIRCC Datasheet(PDF) 28 Page - SMSC Corporation

CIRCC Datasheet(HTML) 28 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL