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CIRCC Datasheet(PDF) 30 Page - SMSC Corporation

Part # CIRCC
Description  Consumer Infrared Communications Controller
PDF  70 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

CIRCC Datasheet(HTML) 30 Page - SMSC Corporation

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Valid Frame, bit 0
The Valid Frame bit reflects the state of the
internal state variable nActive Frame.
When
nActive Frame=0 (active) Valid Frame=1 (active).
When nActive Frame=1 (inactive) Valid Frame=0
(inactive).
Valid Frame is only defined for the
SCE Encoder/Decoders during Transmit and
Receive.
REGISTER BLOCK ONE
Register Block One contains the SCE control
registers (Table 17).
Typically, the controls in
Register Block One are needed to configure the
SCE before message transactions can occur.
Bits and registers marked “reserved” in the table
below cannot be written and return 0s when read.
Programmers must set reserved bits to 0 (zero)
when writing to registers that contain reserved
bits.
Table 17 - Register Block One
Address
Direction
Description
Default
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
R/W
SCE Configuration Register A
'02'hex
aux
ir
block control
bits
half
duplx
tx po-
larity
rx po-
larity
0
0
1
R/W
SCE Configuration Register B
'00'hex
output mux
bits
loop-
back
no
wait
string
move
dma
burst
dma
enable
0
1
0
R/W
FIFO Threshold Register
'00'hex
0
1
1
RO
FIFO COUNT
'00'hex
FC7
FC6
FC5
FC4
FC3
FC3
FC1
FC0
1
0
0
Reserved
1
0
1
Reserved
1
1
0
R/W
SCE Configuration Register C
'03'hex
rsvd
tx pw
limit
reserved
DMA Refresh
Count
SCE Configuration Register A (Address 0)
Auxiliary IR, bit 7
When the Auxiliary IR bit is one and the active
device is routed through the Output Multiplexer to
the IR Port or the COM Port, the transmit signal
also appears at the Auxiliary Port.
Block Control, bits 3 – 6
The Block Control bits select one of the six IrCC
2.0 operational modes (Table 18).
The three
low-order
Block
Control bits are
equivalent to the IR Mode bits in the chip-level
configuration space of earlier devices; e.g., the
FDC37C93x IR Option Register, Serial Port 2,
Logical Device 5, Register 0xF1.
Provisions
have
been
made
in
legacy
devices
to
accommodate IR Mode selection through either
the chip-level configuration registers or the IrCC
2.0 Block Control bits; i.e., the last write from
either source determines the current mode
selection and is visible in both registers.



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