CIRCC datasheet(60/70 Pages) SMSC

60 / 70 page

DRQ Control

In DMA Burst Mode, DRQ remains active until

the entire DMA data block has been transferred,

as indicated by DMA Terminal Count (TC). The

internal

FIFO

Full

signal

can

temporarily

deactivate DRQ if the DMA block has not been

completely transferred but there is no room left in

the FIFO for more data. As soon as the FIFO

Full becomes inactive, DRQ is reasserted. The

internal

Refresh

Interval

signal

can

also

temporarily deactivate DRQ (see the DMA

Refresh Counter on page 59).

Burst Mode Receive

DRQ Control

In DMA Burst Mode, DRQ remains active until

the entire DMA data block has been transferred,

as indicated by DMA Terminal Count (TC).

Since the FIFO Threshold is not used for DMA

transfer cycles, DRQ is asserted as soon as

FIFO Not Empty is true.

FIFO Not Empty can

temporarily deactivate DRQ if the DMA block has

not been completely transferred but there is no

data left in the FIFO to transfer.

As soon as

FIFO

Not

Empty

becomes

true,

DRQ

reasserted.

The internal refresh counter can

also temporarily deactivate DRQ (see the DMA

Refresh Counter on page 59).

DMA Enable

DRQ

I/Ox

nDACK

Refresh Interval

32 clocks

max.

350ns

min.

Disable 32-Clk

Countdown & Reset

32-Clk Counter

Enable 32-Clk

Countdown

DMA Burst

FIGURE 25 - DMA REFRESH COUNT TIMING

DMA Enable

DRQ

FIFO FULL

DMA Burst

Refresh Interval

Tx Enable

TxServReq

FIGURE 26 - DMA BURST MODE TRANSMIT TIMING

CIRCC Datasheet(PDF) 60 Page - SMSC Corporation

CIRCC Datasheet(HTML) 60 Page - SMSC Corporation

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