CIRCC datasheet(48/70 Pages) SMSC

48 / 70 page

In this mode, the user's program will check RCVR

and XMITTER status via the LSR. LSR definitions

for the FIFO Polled Mode are as follows:

Bit 0=1 as long as there is one byte in the

RCVR FIFO.

Bits 1 to 4 specify which error(s) have

occurred.

Character error status is handled

the same way as when in the interrupt mode,

the IIR is not affected since EIR bit 2=0.

Bit 5 indicates when the XMIT FIFO is empty.

Bit 6 indicates that both the XMIT FIFO and

shift register is empty.

Bit 7 indicates whether there are any errors in

the RCVR FIFO.

There is no trigger level reached or timeout

condition indicated in the FIFO Polled Mode,

however, the RCVR and XMIT FIFOs are still fully

capable of holding characters.

Table 28 - Baud Rates Using 1.8462 MHz Clock (24 MHz/13)

DESIRED BAUD

RATE

DIVISOR USED TO

GENERATE 16X CLOCK

PERCENT ERROR DIFFERENCE

BETWEEN DESIRED AND ACTUAL

UART HIGH

SPEED BIT

2304

0.001

1536

110

1047

134.5

857

0.004

150

768

300

384

600

192

1200

1800

2000

0.005

2400

3600

4800

7200

9600

19200

38400

0.030

57600

0.16

115200

0.16

230400

32770

0.16

460800

32769

0.16

Note

1: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.

Note

2: The UART High Speed bit is located in the device configuration space.

CIRCC Datasheet(PDF) 48 Page - SMSC Corporation

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