CIRCC datasheet(59/70 Pages) SMSC

59 / 70 page

Burst (Demand) Mode

DMA Burst mode is enabled by setting the DMA

Burst bit in SCE Configuration Register B.

Demand Mode DMA transfers up to 32 data

bytes for each DRQ (Figure 24).

The CIrCC

guarantees that DRQ relinquishes the ISA bus

after thirty-two DMA I/O read or write cycles to

allow for memory refresh.

DMA Refresh Counter

The DMA Refresh Counter is used to prevent

DRQ from staying active for more than 4, 8, 16,

or 32 I/O cycles at a time (see DMA Refresh

Count, bits 0-1, on page 34).

The counter is stopped and preloaded whenever

DRQ is not active. Once DRQ becomes active,

the counter decrements until zero-count or DRQ

is deactivated.

In Demand Mode, the count-zero condition

always clears DRQ and triggers a Refresh

Interval. The Refresh Interval remains active for

350ns following an inactive nDACK (Figure 25).

If there is more data to transfer, DRQ goes active

again and the cycle repeats.

Single Byte Mode DMA does not use the DMA

Refresh Counter. Table 22 illustrates the DMA

Refresh Count bit encoding; e.g., if D[1:0] = 0,0,

the DMA Refresh Counter will prevent DRQ from

staying active for more than four I/O read/write

cycles at a time.

DMA Enable

DRQ

I/Ox

nDACK

DMA Burst

AEN

FIGURE 24 - DMA BURST MODE TIMING

CIRCC Datasheet(PDF) 59 Page - SMSC Corporation