IRCC2.0 datasheet(28/87 Pages) SMSC

28 / 87 page

Frame Error, bit 5

The Frame Error bit gets set to one when IrDA

framing errors are detected; for example, HDLC

pulse-widths greater than one bit-cell, and invalid

framing fields (see the Framing Errors section on

page 65).

Size Error, bit 4

The Size Error bit is set to one whenever the

IrDA FIR receiver decrements the Rx Data Size

count to zero before the End-Of-Frame, or

whenever the the Brick Wall bit is inactive and

the IrDA FIR transmitter decrements the Tx Data

Size count to zero before FIFO Empty goes

active.

CRC Error, bit 3

The CRC Error bit is set to one following Frame-

Check-Sequence errors in IrDA FIR receive

message frames.

Frame Abort, bit 2

The Frame Abort bit is set to one following; 1) a

forced abort, i.e. after setting the Abort bit to one

in Line Control Register A; 2) an IrDA FIR FIFO

underrun with the Data Done bit inactive during

transmit; 3) an IrDA FIR FIFO Overrun during

receive; 4) framing errors in IrDA FIR payload

data during receive. NOTE: The Frame Abort bit

will not go active during transmit if the Tx Data

Size register decrements to zero when the last

byte is read from the FIFO with the Data Done bit

not set.

Status Register Address, bits 0 - 2 (write-

only)

Three Status Register Address bits control

software access to, and reside at the same

address as, the Line Status Registers.

The

Status Register Address bits are write-only and

occupy bits D0 to D2. To access any one of the

eight Line Status Registers or the Message Byte

Counters (SCE Register Block One, addresses 4

and 5), first write the address of the appropriate

Line Control Register A (Address 4)

FIFO Reset, bit 7

When set to one, the FIFO Reset bit clears the

FIFO Full and Not Empty flags in the 128-byte

SCE FIFO. The FIFO Reset bit is automatically

set to zero following the re-initialization.

Fast, bit 6

The Fast bit controls the state of an uncommitted

IrCC 2.0 output, Fast. The bit is read/write.

General Purpose Data, bit 5

The General Purpose Data bit controls the state

of an uncommitted IrCC 2.0 output, GP Data.

The bit is read/write.

Raw Tx, bit 4

The Raw Tx bit controls the state of the infrared

emitter in Raw IR mode. The bit is read/write.

Raw Rx, bit 3

The Raw Rx bit represents the state of the

infrared detector in Raw IR mode.

The bit is

read-only.

IRCC2.0 Datasheet(PDF) 28 Page - SMSC Corporation

IRCC2.0 Datasheet(HTML) 28 Page - SMSC Corporation

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