IRCC2.0 datasheet(29/87 Pages) SMSC

29 / 87 page

Abort, bit 2

The Abort bit is used to cancel messages in

progress. When the Abort bit is set to one, an

IrDA Abort sequence is sent, the EOM flag is

activated, and the SCE FIFO is cleared.

The

Abort bit is reset to zero following EOM. Abort

can be used during IrDA FIR transmit mode only.

Data Done, bit 1

When set to one, the Data Done bit is used

during transmit to distinguish an end-of-valid-

message-data condition from a FIFO Underrun

that

indicates

incomplete

message

data.

Terminal Count automatically activates the Data

Done

bit

during

DMA

operations.

Note:

The Data Done bit is not activated by TC during

receive operations.

Data Done is automatically

reset to zero following the end of a message only

if the FIFO is empty.

Line Control Register B (Address 5)

SCE Modes, bits 6 - 7

The SCE Modes bits enable the SCE transmitter

and receiver (Table 16). These bits are R/W and

must be manually reset by the host following

IrDA message transactions.

The SCE Modes

bits are automatically reset by the hardware

following Consumer IR messages.

Note: the

SCE Modes bits must be zero for loopback tests.

Table 16 - SCE Modes

MODE DESCRIPTION

Receive/Transmit Disabled (default)

Transmit Mode

Receive Mode

Undefined

Transmit Mode

Transmit mode enables the SCE IrDA FIR and

Consumer IR transmitters whenever TC goes

active, or the FIFO THRESHOLD has been

exceeded (see the Transmit Timing section on

page 61).

In Transmit mode, the SCE FIFO

input is connected to the Host System Data Bus

and the FIFO output is connected to the SCE

transmitter input.

Transmit mode is strictly

software controlled when the IrDA FIR encoders

are active. The Consumer IR encoder will reset

Transmit mode in hardware following the rising

edge

nActive

Frame

following

FIFO

underrun.

Receive Mode

Receive mode enables the SCE IrDA FIR and

Consumer IR receivers (see the Receive Timing

section on page 66). In Receive mode, the SCE

FIFO output is connected to the Host System

Data Bus, the FIFO input is connected to the

SCE receiver output.

Receive mode is strictly

software controlled when the IrDA FIR encoders

are active. The Consumer IR encoder will reset

Receive mode in hardware following the rising

edge

nActive

Frame

following

FIFO

underrun or TC.

SIP Enable, bit 5

If the SIP Enable is one, an SIR Interaction Pulse

occurs every 500ms if an IrDA FIR mode has

been selected and the transmitter or receiver is

not otherwise engaged (see the SIR Interaction

Pulse section on page 19).

Brick Wall, bit 4

When the Brick Wall bit is active the IrCC 2.0

sends back-to-back IrDA FIR frames separated

by the number of additional flags specified in the

brick wall count register (see the Multi-Frame

Window Support section on page 67). The Data

Size register or the Message Byte Counters can

be used when the Brick Wall bit is active to send

back-to-back IrDA FIR frames when the DMA

data block is larger than the IrDA message

length. In this case, if the maximum number of

data bytes according to the Tx Data Size register

Message

Byte

Counter

have

been

IRCC2.0 Datasheet(PDF) 29 Page - SMSC Corporation

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