IRCC2.0 datasheet(68/87 Pages) SMSC

68 / 87 page

When the MFW bit = 0, the Rx Data Size register

used to determine the maximum frame-size

per message in multi-frame windows. To receive

multi-frame windows initialize the DMA controller

with a data block no larger than Rx Data Size

n, where n is the maximum number of message

frames supported in the window. Enable the

appropriate decoder and wait for the window

transfer to complete.

Use the Rx Data Size

the window condition. The Brick Wall Count and

Brick Wall bit have no effect when receiving

multi-frame windows.

Variable Frame-Size Windows

Transmit

When the MFW bit = 1, the Message Byte Count

registers are used to determine the size of

message frames in a multi-frame window. For

variable frame-size windows, each message

frame can have a different size. Variable frame-

size transmit multi-frame windows can occur in

both Brick Walled and non-Brick Walled modes.

Non-Brickwalled MFWs

To support non-Brick Walled variable frame-size

multi-frame windows set the SCE Modes bits to

zero and initialize the DMA controller with a

message block that is the size of all of the

messages to be transferred in the window.

Initialize the Message Byte Count registers with

the

appropriate

message

byte

counts

per

message, choose the appropriate encoder, start

the transmitter, and wait for an EOM Interrupt.

Reset and then re-enable the transmitter n times,

where n is the number of message frames in the

window,

until

the

DMA

block

has

been

transferred. Reset the FIFO Threshold for the

last frame, if necessary.

Brickwalled MFWs

To support Brick Walled variable frame-size

multi-frame windows set the SCE Modes bits to

zero and initialize the DMA controller with a

message block that is the size of all of the

messages to be transferred in the window.

Initialize the Message Byte Count registers with

the

appropriate

message

byte

counts

per

message,

choose

the

appropriate

encoder,

initialize the Brick Wall Count, and set the Brick

Wall bit. Start the transmitter and wait for n EOF

interrupts, where n is the number of message

frames in the window, until the DMA block has

been transferred.

Receive

When the MFW bit = 1, the Rx Data Size register

is used to determine the maximum frame-size

per message in multi-frame windows and the

Message Byte Count registers maintain the

numbers of bytes in each message per frame for

up to eight frames.

To receive multi-frame

windows initialize the DMA controller with a data

block no larger than Rx Data Size

× n, where n is

the

maximum

number

message

frames

supported in the window. Enable the appropriate

decoder and wait for the window transfer to

complete. Use the Message Byte Counts, the Rx

Data Size and the Line Status registers to

evaluate the window condition. The Brick Wall

Count and Brick Wall bit have no effect when

receiving multi-frame windows.

LOOPBACK MODE

Loopback mode allows diagnostic testing of the

IrDA FIR and Consumer IR encoders. Loopback

tests require that the SCE FIFO be used for both

transmit and receive modes, simultaneously.

The Data Size registers are used to constrain the

Loopback test. Brick Walled messages are not

supported in Loopback mode.

Initialization

The FIFO must be loaded with the appropriate

transmit data while the Block Control bits in SCE

Configuration Register A are set to the required

transfer mode with the SCE MODES bits set to

Transmit/Receive Disabled. Enough room must

remain in the FIFO for receive data.

The

Loopback

Transmit

CRC

bit

(D6)

SCE

Configuration Register B must be initialized for

the appropriate CRC response during loopback

testing.

The Data Size registers must be

IRCC2.0 Datasheet(PDF) 68 Page - SMSC Corporation

IRCC2.0 Datasheet(HTML) 68 Page - SMSC Corporation

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