IRCC2.0 datasheet(32/87 Pages) SMSC

32 / 87 page

registers (Table 18).

Typically, the controls in

SCE before message transactions can occur.

Bits and registers marked “reserved” in the table

below cannot be written and return 0s when read.

Programmers must set reserved bits to 0 (zero)

when writing to registers that contain reserved

bits.

Table 18 - Register Block One

Address

Directio

Description

Default

R/W

SCE Configuration Register A

'02'hex

aux

block control

bits

half

duplx

tx po-

larity

rx po-

larity

R/W

SCE Configuration Register B

'00'hex

output mux

bits

loop-

back

lpbck

tx crc

wait

string

move

dma

burst

dma

enable

R/W

FIFO Threshold Register

'00'hex

FIFO COUNT

'00'hex

FC7

FC6

FC5

FC4

FC3

FC1

FC0

R/W

Message Byte-Count (low byte)

'00'hex

MBC

R/W

Message Byte-Count (high byte)

'00'hex

reserved

MBC

R/W

SCE Configuration Register C

'03'hex

MFW

tx pw

limit

rx pw

reject

reserved

DMA Refresh

Count

SCE Configuration Register A (Address 0)

Auxiliary IR, bit 7

When the Auxiliary IR bit is one and the active

device is routed through the Output Multiplexer to

the IR Port or the COM Port, the transmit signal

also appears at the Auxiliary Port.

Block Control, bits 3 - 6

The Block Control bits select one of the eight

IrCC 2.0 operational modes (Table 19).

The

three low-order Block Control bits are equivalent

to the IR Mode bits in the chip-level configuration

space of earlier devices; e.g., the FDC37C93x IR

Option Register, Serial Port 2, Logical Device 5,

Provisions have been made in

legacy

devices

accommodate

Mode

selection

through

either

the

chip-level

configuration registers or the IrCC 2.0 Block

Control bits; i.e., the last write from either source

determines the current mode selection and is

visible in both registers.

IRCC2.0 Datasheet(PDF) 32 Page - SMSC Corporation

IRCC2.0 Datasheet(HTML) 32 Page - SMSC Corporation

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