IRCC2.0 datasheet(43/87 Pages) SMSC

43 / 87 page

programmable from 0ms to 25.5ms in 100

µs

intervals. The IR Half Duplex Timeout register

behaves

the

other

Legacy

Chip-Level

Controls described in the Interface Description;

i.e., the IR Half Duplex Timeout is uniformly

updated in the IrCC 2.0 and the chip-level

configuration

registers

when

either

set

registers are explicitly written using IOW or

following a POR. IrCC 2.0 software resets do not

affect the IR Half Duplex Timeout register. The

effects of the IR Half Duplex Timeout apply to the

SCE receiver/transmitter as well as the ACE

receiver/transmitter. The IR Half Duplex Timeout

applies to all SCE encoder/decoder types except

for the RAW Mode.

SCE Transmit Delay Timer Register

(Address 2)

SCE Transmit Delay Timer, bits 0 - 6

The SCE Transmit Delay Timer delays the

internal activation of the SCE transmitter (Tx

Enable)

programmable

time

interval

following a transmit command (see the Transmit

Timing

section

page

61).

Transmit

commands are issued using the SCE Modes

bits.

The

SCE

Transmit

Delay

Timer

programmable from 0ms to 12.70ms in 100

µS

intervals. The relationship of the SCE Transmit

Delay Timer Register (Treg) to the SCE Transmit

Delay Time (Tdelay) is given by:

Tdelay = Treg • 100µS

The SCE Transmit Delay Timer applies to all

SCE encoder types except for the RAW Mode

encoder.

IRCC2.0 Datasheet(PDF) 43 Page - SMSC Corporation

IRCC2.0 Datasheet(HTML) 43 Page - SMSC Corporation

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