IRCC2.0 datasheet(71/87 Pages) SMSC

71 / 87 page

BUS INTERFACE I/O

The Bus Interface I/O block contains a 128-byte

FIFO, DMA/Interrupt logic, and multiplexers to

control access to the FIFO and the ISA Bus

(Figure 36).

The Databus Multiplexer provides exclusive ISA

Bus access to either the 16C550A UART or the

IrCC 2.0 SCE depending on the state of Block

Control bits.

Disabled blocks are disconnected

from the ISA Bus.

FIFO MULTIPLEXER

SCE FIFO Access

The FIFO Multiplexer controls the configuration

of the SCE FIFO in the Bus Interface I/O Block.

This configuration can be inferred from the state

of the SCE Modes bits in Line Control Register

When

the

transmit/receive

modes

are

disabled, or the transmit mode is enabled, the

FIFO is configured for transmit, otherwise, the

FIFO is configured for receive.

The signal

Transmit in Figure 36, above, can be satisfied by

the inverse of the SCE Modes msb; e.g., nD7.

HOST FIFO Access

The host always has read access to the FIFO,

regardless of the state of the SCE Modes bits, or

the Loopback bit. The host has write access to

the FIFO when the Loopback bit is inactive and

the transmit/receive modes are disabled or the

Transmit mode is enabled.

128-BYTE SCE FIFO

FIFO Timing & Controls

The FIFO requires interleaved access timing to

allow simultaneous FIFO data reads and data

FIFO

Multiplexer

128-byte

FIFO

Transmit

Loopback

SCE

Databus Multiplexer

16550A UART

ISA Bus

Loopback

Transmit

Function

FIFO In to SCE Rx

FIFO Out to Host Bus

FIFO In to Host Bus

FIFO Out to SCE Tx

FIFO In to SCE Rx

FIFO Out to SCE Tx

I/O & Interrupt

Control

FIGURE 36 - BUS INTERFACE I/O BLOCK

IRCC2.0 Datasheet(PDF) 71 Page - SMSC Corporation

IRCC2.0 Datasheet(HTML) 71 Page - SMSC Corporation

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