IRCC2.0 datasheet(69/87 Pages) SMSC

69 / 87 page

properly initialized to constrain the loopback

function

that

received

data

not

re-

transmitted.

The

Rx Data Size register is

required for Consumer IR Loopback tests; the Tx

Data Size register is required for IrDA FIR

Loopback

tests.

Note:

for

Consumer

Loopback tests the value in the Rx Data Size

of bytes transferred. Proper programming of the

Tx Data Size register depends upon the state of

the CRC Select and Loopback Tx CRC bits (see

the Tx Data Size High, bits 0-3, on page 40). If

the hardware CRC generator is used, the Tx

Data Size register will contain the total number of

message bytes minus the number of CRC bytes.

If the hardware CRC generator is not used, the

Tx Data Size register will contain the total

number of message bytes including the number

of CRC bytes. The FIFO Threshold is not used

for loopback tests.

The Tx Polarity and Rx

Polarity bits must be set to the same state for

loopback tests.

Set the Loopback bit in SCE

Configuration Register B to begin the loopback

test.

Retrieving Results

The loopback test data can be read from the

FIFO immediately following the End-of-Message;

i.e., the Loopback bit does not need to be reset,

nor does the FIFO need to be explicitly re-

configured for ISA bus access.

AUTOMATIC TRANSCEIVER CONTROL

The ATC register, address 0 in SCE Register

Block Five, is used to automatically program the

data

rates

for

the

IBM/TEMIC

transceiver

modules using the TX and IRMODE transceiver

pins (Figure 11).

The IBM/TEMIC modules

power-up in low speed mode. Low speed mode

covers speeds up to and including 1.152 Mbps.

The

IBM/TEMIC

transceiver

speed

change

timing is shown in Figure 35.

The transceiver

latches the state of the TX input pin on the falling

edge of IRMODE. The TX pin is the IrDA FIR TX

port signal, IRMODE comes from the G.P. DATA

port.

The ATC must not interfere with these

signals except when the ATC is enabled and

programming is in progress (ATC nProg/Ready =

0). To use the ATC to program the IBM/TEMIC

transceiver for fast mode set the ATC ENABLE

bit high, set the ATC SPEED bit high, and set the

ATC nPROG/READY bit low. When the ATC

nPROG/READY bit goes high the programming

cycle has ended (Figure 34). To use the ATC to

program the IBM/TEMIC transceiver for slow

mode set the ATC ENABLE bit high, set the ATC

SPEED bit low, and set the ATC nPROG/READY

bit low. When the ATC nPROG/READY bit goes

high the programming cycle has ended (Figure

34). When ATC nPROG/READY is low the GP

DATA signal is disabled and has no affect on

IRMODE until nPROG/READY goes high.

shown in Figure 35 the ATC Enable, ATC Speed

and ATC nPROG/READY can be activated

simultaneously in one write to D7 - D5, Address

0, SCE Register Block Five.

APPLICATION NOTE: The ATC must only be

enabled

the

IRMODE/IRRX3

programmed as an output.

IRCC2.0 Datasheet(PDF) 69 Page - SMSC Corporation

IRCC2.0 Datasheet(HTML) 69 Page - SMSC Corporation

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