IRCC2.0 datasheet(5/87 Pages) SMSC

5 / 87 page

Table 4 - G. P. Port Signals

NAME

SIZE (BITS)

TYPE

DESCRIPTION

Fast

Output

General Purpose Data

GP Data

Output

General Purpose Data

Fast

The Fast pin always reflects the state of Fast, bit

6 of SCE Line Control Register A. The state of

Fast is independent of the IrCC 2.0 Block

Controls or the Output Multiplexer. The Fast pin

can be used at the chip level for IR Transceiver

configuration.

GP Data

The G.P. Data pin typically reflects the state of

General Purpose Data, bit 5 of SCE Line Control

The

state

G.P.

Data

independent of the IrCC 2.0 Block Controls or

the Output Multiplexer but will depend on the

ATC during transceiver programming cycles (see

the Automatic Transceiver Control section on

page 69).

Table 5 - HOST Signals

NAME

SIZE (BITS)

TYPE

DESCRIPTION

D0-D7

Bi-directional

Host Data Bus

A0-A2

Input

IrCC 2.0 Register Address Bus

nIOR

Input

ISA I/O Read

nIOW

Input

ISA I/O Write

AEN

Input

ISA Address Enable

DRQ

Output

DMA Request

nDACK

Input

ISA DMA Acknowledge

Input

ISA DMA Terminal Count

IRQ

Output

Interrupt Request

IOCHRDY

Output

ISA I/O Channel Ready

nSRDY

Output

ISA Synchronous Ready (Zero Wait State)

IRCC2.0 Datasheet(PDF) 5 Page - SMSC Corporation

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