IRCC2.0 datasheet(67/87 Pages) SMSC

67 / 87 page

MULTI-FRAME WINDOW SUPPORT

The IrCC 2.0 can send and receive up to eight

unacknowledged data frames, i.e. a multi-frame

window.

Sending and receiving multi-frame

windows is accomplished with DMA blocks that

are larger than the size of an individual IrDA

message frame.

The MFW bit (see the SCE

Configuration Register C (Address 6) on page

32) determines whether multi-frame windows use

the Tx Data Size Register or the Message Byte

Count Registers to determine the frame size per

message in multi-frame windows. All multi-frame

window support can occur in both Brick Walled

and non-Brick Walled modes.

Fixed Frame-Size Windows

Transmit

When MFW bit = 0, the Tx Data Size register is

used to determine the size of message frames in

a multi-frame window.

For fixed frame-size

windows all message frames will be the same

size except for the last frame which may be

smaller.

Fixed frame-size transmit multi-frame

windows can occur in both Brick Walled and non-

Brick Walled modes.

Non-Brickwalled MFWs

To support non-Brick Walled fixed frame-size

multi-frame windows set the SCE Modes bits to

zero and initialize the DMA controller with a

message block that is the size of all of the

messages to be transferred in the window, i.e.,

no larger than Tx Data Size

× n, where n is the

number of message frames in the window.

Initialize the Tx Data Size register, choose the

appropriate encoder, start the transmitter, and

wait for an EOM interrupt. Reset and then re-

enable the transmitter DMA block-size

÷ Tx Data

Size times, until all of the messages in the DMA

block have been transferred.

Reset the FIFO

Threshold for the last frame, if necessary.

Brickwalled MFWs

To support Brick Walled multi-frame windows set

the SCE Modes bits to zero and initialize the

DMA controller with a data block that is the size

of all of the messages to be transferred in the

window, i.e., no larger than Tx Data Size

× n,

where n is the number of message frames in the

window.

Choose the appropriate encoder,

initialize the Brick Wall Count, and set the Brick

Wall bit. Start the transmitter once only and wait

for DMA block-size

÷ Tx Data Size EOF

interrupts

until

the

DMA

block

has

been

transferred.

Receive

FIFO Full

EOM Interrupt

Rx Enable

nActive Frame

Active Frame Int.

Zero Detect

Overrun

FIGURE 33 - REMOTE CONTROL RX ABORT ON OVERRUN

IRCC2.0 Datasheet(PDF) 67 Page - SMSC Corporation

IRCC2.0 Datasheet(HTML) 67 Page - SMSC Corporation

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