IRCC2.0 datasheet(40/87 Pages) SMSC

40 / 87 page

registers.

These registers control the IrDA

message

framing

parameters,

HDLC

clock

speed, and hardware CRC selection.

The

registers

are

read/write.

Bits

and

registers

marked “reserved” in the table below cannot be

written and return 0s when read. Programmers

must set reserved bits to 0 (zero) when writing to

registers that contain reserved bits.

Table 28 - SCE Register Block Four

Address

Direction

Description

Default

R/W

IrDA Control Register

'C0'hex

1.152

select

crc

select

reserved

bof count

(high nibble)

R/W

bof count (low byte)

'00'hex

R/W

brick wall count (low byte)

'00'hex

R/W

brick wall count (high nibble)

tx data size (high nibble)

'00'hex

R/W

tx data size (low byte)

'00'hex

R/W

reserved

rx data size (high nibble)

'00'hex

R/W

rx data size (low byte)

'00'hex

IrDA Control Register/BOF Count High

(Address 0)

1.152 Select, bit 7

When the 1.152 Select bit is one, the IrDA 1.152

Mbps HDLC-type FIR data rate is selected.

Otherwise the 0.576 Mbps rate is chosen. This

bit only applies to the SCE clock when the Block

Control bits select Mode 2, IrDA HDLC.

CRC Select, bit 6

When the CRC Select bit is one, a hardware-

generated CRC is appended to the frame

payload

data

during

IrDA

FIR

message

transactions (Table 22).

BOF Count High, bits 0 - 3

The

BOF

Count

specifies

the

number

additional

flags

that

are

used

BOF

sequence. For example, at 1.152 Mbps, insert

the

BOF

Count

number

additional

flag

characters ('7E'hex) at the start of every frame,

excluding brick walled frames.

At 4 Mbps insert

the BOF Count number of additional PA bytes at

the start of every frame, excluding brick walled

frames. The BOF Count is a 12 bit value. This

upper nibble.

BOF Count Low (Address 1)

The BOF Count Low register is the lower byte of

the BOF Count.

Brick Wall Count Low (Address 2)

The Brick Wall Count register specifies the

number of additional interframe padding flags

used for brick walled messages. The Brick Wall

Count is a 12 bit value. The Brick Wall Count

Low register is the Brick Wall Count lower byte.

BW Count High/Tx Data Size High

(Address 3)

Brick Wall Count High, bits 4 - 7

The BW Count High register is the upper nibble

of the Brick Wall Count.

Tx Data Size High, bits 0 - 3

The Tx Data Size register specifies the IrLAP-

negotiated maximum number of payload data

bytes per IrDA transmit message frame if

software

CRC

selected,

the

IrLAP-

negotiated maximum number of payload data

bytes minus the number of CRC bytes if

hardware CRC is selected. This register is used

to 1) constrain the transmitter to a valid IrDA

IRCC2.0 Datasheet(PDF) 40 Page - SMSC Corporation

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