AM62A7 datasheet(175/238 Pages) TI1

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7.10.5.16.1.4 Default Speed Mode

Table 7-86, Figure 7-72, Table 7-87, and Figure 7-73 present timing requirements and switching characteristics

for MMC0 – Default Speed Mode.

Table 7-86. Timing Requirements for MMC0 – Default Speed Mode

see Figure 7-72

NO.

MIN

MAX

UNIT

DS1

tsu(cmdV-clkH)

Setup time, MMC0_CMD valid before MMC0_CLK rising edge

2.15

DS2

th(clkH-cmdV)

Hold time, MMC0_CMD valid after MMC0_CLK rising edge

1.67

DS3

tsu(dV-clkH)

Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge

2.15

DS4

th(clkH-dV)

Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge

1.67

MMC[ ]_CLK

[ ]_

CMD

MMC

DAT

[ ]_

[3:0]

DS1

DS2

DS3

DS4

Figure 7-72. MMC0 – Default Speed – Receive Mode

Table 7-87. Switching Characteristics for MMC0 – Default Speed Mode

see Figure 7-73

NO.

PARAMETER

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

MHz

DS5

tc(clk)

Cycle time, MMC0_CLK

DS6

tw(clkH)

Pulse duration, MMC0_CLK high

18.7

DS7

tw(clkL)

Pulse duration, MMC0_CLK low

18.7

DS8

td(clkL-cmdV)

Delay time, MMC0_CLK falling edge to MMC0_CMD transition

- 1.8

2.2

DS9

td(clkL-dV)

Delay time, MMC0_CLK falling edge to MMC0_DAT[3:0] transition

- 1.8

2.2

MMC[ ]_CLK

MMC

CMD

[ ]_

MMC

DAT

[ _

[3:0]

D 5

D 7

D 8

D 9

DS6

Figure 7-73. MMC0 – Default Speed – Transmit Mode

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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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